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MX28F1000P Datasheet(PDF) 5 Page - List of Unclassifed Manufacturers

Part No. MX28F1000P
Description  1M-BIT [128K x 8] CMOS FLASH MEMORY
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Maker  ETC [List of Unclassifed Manufacturers]
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MX28F1000P Datasheet(HTML) 5 Page - List of Unclassifed Manufacturers

 
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P/N: PM0340
REV. 1.6, JAN. 19, 1999
MX28F1000P
AUTOMATIC PROGRAMMING
The MX28F1000P is byte programmable using the
Automatic Programming algorithm.
The Automatic
Programming algorithm does not require the system to
time out or verify the data programmed. The typical
room temperature chip programming time of the
MX28F1000P is less than 5 seconds.
AUTOMATIC CHIP ERASE
The device may be erased using the Automatic Erase
algorithm. The Automatic Erase algorithm automati-
cally programs the entire array prior to electrical erase.
The timing and verification of electrical erase are
controlled internal to the device.
AUTOMATIC BLOCK ERASE
The MX28F1000P is block(s) erasable using MXIC's
Auto Block Erase algorithm. Block erase modes allow
blocks of the array to be erased in one erase cycle.
The Automatic Block Erase algorithm automatically
programs the specified block(s) prior to electrical
erase. The timing and verification of electrical erase
are controlled internal to the device.
AUTOMATIC PROGRAMMING ALGORITHM
MXIC's Automatic Programming algorithm requires
the user to only write a program set-up command and
a program command (program data and address). The
device automatically times the programming pulse
width, provides the program verify, and counts the
number of sequences. A status bit similar to DATA
polling and a status bit toggling between consecutive
read cycles, provide feedback to the user as to the
status of the programming operation.
MXIC's Automatic Erase algorithm requires the user to
only write an erase set-up command and erase com-
mand. The device will automatically pre-program and
verify the entire array. Then the device automatically
times the erase pulse width, provides the erase verify,
and counts the number of sequences. A status bit
similar to DATA polling and a status
bit toggling
between consecutive read cycles, provide feedback to
the user as to the status of the erase operation.
Commands are written to the command register using
standard microprocessor write timings. Register con-
tents serve as inputs to an internal state-machine
which controls the erase and programming circuitry.
During write cycles, the command register internally
latches address and data needed for the programming
and erase operations. For system design simplifica-
tion, the MX28F1000P is designed to support either
WE or CE controlled writes. During a system write
cycle, addresses are latched on the falling edge of WE
or CE whichever occurs last. Data is latched on the
rising edge of WE or CE whichever occur first. To
simplify the following discussion, the WE pin is used as
the write cycle control pin throughout the rest of this
text. All setup and hold times are with respect to the
WE signal.
MXIC's Flash technology combines years of EPROM
experience to produce the highest levels of quality, relia-
bility, and cost effectiveness. The MX28F1000P electri-
cally erases all bits simultaneously using Fowler-Nord-
heim tunneling. The bytes are programmed one byte at
a time using the EPROM programming mechanism of hot
electron injection.
AUTOMATIC ERASE ALGORITHM
INDEX


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