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TUSB213IRGYR Datasheet(PDF) 11 Page - Texas Instruments

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Part # TUSB213IRGYR
Description  USB 2.0 High Speed Signal Conditioner
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TUSB213IRGYR Datasheet(HTML) 11 Page - Texas Instruments

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11
TUSB213
www.ti.com
SLLSEX6A – AUGUST 2017 – REVISED AUGUST 2017
Product Folder Links: TUSB213
Submit Documentation Feedback
Copyright © 2017, Texas Instruments Incorporated
Typical Application (continued)
8.2.1 Design Requirements
For this design example, use the parameters shown in the table below.
Table 3. Design Parameters
PARAMETER
VALUE
VCC (4.4 V to 5.5 V)
5 V
I2C support required in system (Yes/No)
No
AC Boost
REQ
Level
AC Boost Level 2:
REQ = 3.83 k
0-Ω
0
1.69k ±1%
1
3.83k ± 1%
2
DNI
3
DC Boost
RDC1
RDC2
Level
Mid DC Level:
RDC1 = DNI
RDC2 = DNI
22k - 47k Ω
Do Not Install (DNI)
40mV Low DC boost
DNI
DNI
60mV Mid DC boost
47k ohms
24k ohms
80mV High DC boost
8.2.2 Detailed Design Procedure
TUSB213 requires a valid reset signal as described in the power supply recommendations section. The capacitor
at RSTN pin is not required if a microcontroller drives the RSTN pin according to recommendations.
VREG pin is the internal LDO output that requires a 0.1-μF external capacitor to GND to stabilize the core.
The ideal AC boost setting is dependent upon the signal chain loss characteristics of the target platform. The
general recommendation is to start with AC boost level 0, and then increment to AC boost level 1, etc. if
permissible. Same applies to the DC Boost setting where it is recommended to plan for the required pads or
connections to change boost settings, but to start with DC boost level 1.
In order for the TUSB213 to recognize any change to the AC and DC Boost settings, the RSTN pin must be
toggled. This is because the configuration is latched on power up and the inputs are ignored thereafter.
NOTE
The TUSB213 compensates for DC attenuation in the signal path according to the
configuration of the DC_BOOST pin. This pin is not 5V tolerant and therefore when
selecting the highest DC boost level, the voltage level at DC_BOOST pin must be less
than 3.6V.
Placement of the device is also dependent on the application goal. Table 4 summarizes our recommendations.
Table 4. Platform Placement Guideline
PLATFORM GOAL
SUGGESTED DEVICE PLACEMENT
Pass USB Near End Mask
Close to measurement point
Pass USB Far End Eye Mask
Close to USB PHY
Cascade multiple devices to improve device enumeration
Midway between each USB interconnect


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