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TIC12400-Q1 Datasheet(PDF) 52 Page - Texas Instruments

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Part # TIC12400-Q1
Description  24-Input Multiple Switch Detection Interface (MSDI) With Integrated ADC and Adjustable Wetting Current for Automotive Systems
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TIC12400-Q1 Datasheet(HTML) 52 Page - Texas Instruments

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TIC12400-Q1
SCPS260 – AUGUST 2017
www.ti.com
Product Folder Links: TIC12400-Q1
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Copyright © 2017, Texas Instruments Incorporated
Table 13. INT_STAT Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
4
TSD
RC
0h
0h = No temperature Shutdown event occurred or the event status
got cleared after a READ command was executed on the INT_STAT
register.
1h = Temperature Shutdown event occurred or cleared.
When the TSD bit is flagged to logic 1, it indicates the temperature
shutdown event has occurred. The bit is also flagged to logic 1 when
the event clears. For more details about the temperature shutdown
operation, please refer to section Temperature shutdown (TSD)
3
SSC
RC
0h
0h = No switch state change occurred or the status got cleared after
a READ command was executed on the INT_STAT register.
1h = Switch state change occurred.
The Switch State Change (SSC) bit indicates whether input
threshold crossing has occurred from switch inputs IN0 to IN23. This
bit is also flagged to logic 1 after the first polling cycle is completed
after device polling is triggered.
2
PRTY_FAIL
RC
0h
0h = No parity error occurred in the last received SI stream or the
error status got cleared after a READ command was executed on
the INT_STAT register.
1h = Parity error occurred.
When the PRTY_FAIL bit is flagged to logic 1, it indicates the last
SPI Slave In (SI) transaction has a parity error. The device uses odd
parity. If the total number of ones in the received data (including the
parity bit) is an even number, the received data is discarded. The
value of this register bit is mirrored to the PRTY_FLAG SPI status
flag.
1
SPI_FAIL
RC
0h
0h = 32 clock pulse during a CS = low sequence was detected or the
error status got cleared after a READ command was executed on
the INT_STAT register.
1h = SPI error occurred
When the SPI_FAIL bit is flagged to logic 1, it indicates the last SPI
Slave In (SI) transaction is invalid. To program a complete word, 32
bits of information must be entered into the device. The SPI logic
counts the number of bits clocked into the IC and enables data
latching only if exactly 32 bits have been clocked in. In case the
word length exceeds or does not meet the required length, the
SPI_FAIL bit is flagged to logic 1, and the data received is
considered invalid. The value of this register bit is mirrored to the
SPI_FLAG SPI status flag. Note the SPI_FAIL bit is not flagged if
SCLK is not present.
0
POR
RC
1h
0h = no Power-On-Reset (POR) event occurred or the status got
cleared after a READ command was executed on the INT_STAT
register.
1h = Power-On-Reset (POR) event occurred.
The Power-On-Reset (POR) interrupt bit indicates whether a reset
event has occurred. A reset event sets the registers to their default
values and re-initializes the device state machine. This bit is
asserted after a successful power-on-reset, hardware reset, or
software reset. The value of this register bit is mirrored to the POR
SPI status flag.


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