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TIC12400-Q1 Datasheet(PDF) 27 Page - Texas Instruments |
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TIC12400-Q1 Datasheet(HTML) 27 Page - Texas Instruments |
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27 / 127 page  27 TIC12400-Q1 www.ti.com SCPS260 – AUGUST 2017 Product Folder Links: TIC12400-Q1 Submit Documentation Feedback Copyright © 2017, Texas Instruments Incorporated The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the INT_STAT register has been read during CS low. The TIC12400-Q1 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above TTW- THYS. The status bit TW_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature warning condition exists. If desired, the reduction of wetting current down to 2mA setting (from 10 mA or 15 mA) can be disabled by setting the TW_CUR_DIS_CSO or TW_CUR_DIS_CSI bit in the CONFIG register to 1. The interrupt is still generated (INT asserted low and INT_STAT interrupt register is updated) when the temperature warning event occurs but the wetting current is not reduced. This setting applies to both the polling and continuous mode operation. Note if the feature is enabled, switch detection result might be impacted upon TTW event if the wetting current is reduced to 2mA from 10mA or 15mA. When the temperature drops below TTW- THYS, the INT pin is asserted low (if released previously) to notify the microcontroller that the temperature warning condition no longer exists. The TW bit of the interrupt register INT_STAT is flagged logic 1. The TW_STAT bit in the IN_STAT_MISC register is de-asserted back to logic 0. The device resumes operation using the current programmed settings (regardless of the INT and CS status). 8.3.10.2 Temperature Shutdown (TSD) After the device enters TW condition, if the junction temperature continues to rise and goes above the temperature shutdown threshold (TTSD), the TIC12400-Q1 enters the Temperature Shutdown (TSD) condition and performs the following operations: 1. Opens all the switches connected to the current sources/sinks to prevent any further heating due to excessive current flow. 2. Generate an interrupt by asserting the INT pin (if not already asserted) low and flag the TSD bit in the INT_STAT register to logic 1. The TEMP bit in the SPI flag is also flagged to logic 1 for all SPI transactions. 3. The TSD_STAT bit of the IN_STAT_MISC register is flagged to logic 1. The TW_STAT bit also stays at logic 1. 4. SPI communication stays on and all register settings stay intact without resetting. Previous switch status, if needed, can be retrieved without any interruption. 5. Maintain the setting as long as the junction temperature stays above TTSD- THYS. The INT pin is released and the INT_STAT register content is cleared on the rising edge of CS provided the INT_STAT register has been read during CS low. The TIC12400-Q1 continues to monitor the temperature, but does not issue further interrupts if the temperature continues to stay above TTSD - THYS. The status bit TSD_STAT in register IN_STAT_MISC continues to stay at logic 1 as long as the temperature shutdown condition exists. When the temperature drops below TTSD - THYS, the INT pin is asserted low (if released previously) to notify the microcontroller that the temperature shutdown condition no longer exists. The TSD bit of the interrupt register INT_STAT is flagged logic 1. In the IN_STAT_MISC register, the TSD_STAT bit is de-asserted back to logic 0, while the TW_STAT bit stays at logic 1. The device resumes operation using the wetting current setting described in section Temperature Warning if the temperature stays above TTW - THYS. Note the polling restarts from the first enabled channel and the SSC interrupt is generated at the end of the first polling cycle. The detected switch status from the first polling cycle becomes the default switch status for subsequent polling. 8.3.11 Parity Check And Parity Generation The TIC12400-Q1 uses parity bit check to ensure error-free data transmission from/to the SPI master. The device uses odd parity, for which the parity bit is set so that the total number of ones in the transmitted data on SO (including the parity bit) is an odd number (i.e. Bit0 ⊕ Bit1 ⊕ … ⊕ Bit30 ⊕ Bit31⊕ Parity = 1). The device also uses odd parity check after receiving data on SI from the SPI master. If the total number of ones in the received data (including the parity bit) is an even number the received data is discarded. The INT will be asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1 to notify the host that transmission error occurred. The PRTY_FAIL flag is also asserted during SPI communications. |
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