HM62864 datasheet(13/15 Pages) ETC | 65536-word 쨈 8-bit High Speed CMOS Static RAM

Part #	HM62864

Description	65536-word 쨈 8-bit High Speed CMOS Static RAM

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HM62864 Series

13

Low V

CC Data Retention Characteristics (Ta = 0 to +70°C)

This characteristics is guaranteed only for L-version.

Parameter

Symbol

Min

Typ

*1

Max

Unit

Test conditions

*5

V

CC for data retention

V

DR

2.0

—

5.5

V

0 V

≤ Vin ≤ V

CC, (1) or (2)

(1)

CS1

≥ V

CC – 0.2 V,

CS2

≥ V

CC – 0.2 V

(2) 0 V

≤ CS2 ≤ 0.2 V

Data retention current

I

CCDR

—

0.1

30

*2

µAV

CC = 3.0 V, 0 V ≤ Vin ≤ VCC, (1) or (2)

(1)

CS1

≥ V

CC – 0.2 V, CS2 ≥ V CC – 0.2V

(2) 0 V

≤ CS2 ≤ 0.2 V

I

CCDR

—

0.1

10

*3

µA

Chip deselect to data

retention time

t

CDR

0

——

ns

See retention waveform

Operation recovery time

t

R

t

RC

*4

——

ns

Notes: 1. Typical values are at V

CC = 3.0 V, Ta = 25°C and not guaranteed.

2. 10

µA max at Ta = 0 to 40°C.

3. This characteristics guaranteed for only L-SL version. 3

µA max at Ta = 0 to 40°C.

4. t

RC = Read cycle time.

5. CS2 controls address buffer,

WE buffer, CS1 buffer, OE buffer, and Din buffer. If CS2 controls

data retention mode, Vin levels (address,

WE, OE, CS1, I/O) can be in the high impedance

state. If

CS1 controls data retention mode, CS2 must be CS2

≥ V

CC – 0.2 V or 0 V ≤ CS2 ≤ 0.2

V. The other input levels (address,

WE, OE, I/O) can be in the high impedance state.

Low V

CC Data Retention Timing Waveform (1) (

CS1 Controlled)

CC

V

4.5 V

2.2 V

0 V

CS1

tCDR

tR

CS1

V

– 0.2 V

CC

≥

DR1

V

Data retention mode

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