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PSN74LVC1G38DPWR Datasheet(PDF) 10 Page - Texas Instruments |
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PSN74LVC1G38DPWR Datasheet(HTML) 10 Page - Texas Instruments |
10 / 19 page 1 2 4 A B Y 10 SN74LVC1G38 SCES538E – JANUARY 2004 – REVISED AUGUST 2017 www.ti.com Product Folder Links: SN74LVC1G38 Submit Documentation Feedback Copyright © 2004–2017, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The SN74LVC1G38 device is designed for 1.65-V to 5.5-V VCC operation. This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function Y = A × B or Y = A + B in positive logic. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. 8.2 Functional Block Diagram Figure 4. Logic Diagram (Positive Logic) 8.3 Feature Description 8.3.1 High-Drive Open-Drain Output The open-drain output allows the device to sink current when the output is LOW and maintains a high impedance state when the output is HIGH. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all times. 8.3.2 Standard CMOS Inputs Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input. |
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