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NS16C2552TVS/NOPB Datasheet(PDF) 6 Page - Texas Instruments |
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NS16C2552TVS/NOPB Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 53 page  NS16C2552, NS16C2752 SNLS238D – AUGUST 2006 – REVISED APRIL 2013 www.ti.com Register Set There are two identical register sets, one for each channel, in the DUART. All register descriptions in this section apply to the register sets in both channels. To clarify the descriptions of transmission and receiving operations, the nomenclatures through out this documentation are as follows: • Frame - Refers to all the bits between Start and Stop. • Character or word - The payload of a frame, between 5 to 8 bits. • “!=” - Not equal to. • Res - Reserved bit. The address and control pins to register selection is summarized in Table 1. Table 1. Basic Register Addresses DLAB1 CHSL A2 A1 A0 Register 0 1 0 0 0 Receive Buffer (Read), Transmitter Holding Register (Write) 0 1 0 0 1 Interrupt Enable 0 1 0 1 0 Interrupt Identification (Read) 0 1 0 1 0 FIFO Control (Write) C H x 1 0 1 1 Line Control A x 1 1 0 0 Modem Control N N x 1 1 0 1 Line Status (Read) E x 1 1 1 0 Modem Status (Read) L 1 x 1 1 1 1 Scratchpad 1 1 0 0 0 Divisor Latch (Least Significant Byte) 1 1 0 0 1 Divisor Latch (Most Significant Byte) 1 1 0 1 0 Alternate Function DLAB1 CHSL A2 A1 A0 Register 0 0 0 0 0 Receive Buffer (Read), Transmitter Holding Register (Write) 0 0 0 0 1 Interrupt Enable 0 0 0 1 0 Interrupt Identification (Read) C 0 0 0 1 0 FIFO Control (Write) H A x 0 0 1 1 Line Control N x 0 1 0 0 Modem Control N x 0 1 0 1 Line Status (Read) E L x 0 1 1 0 Modem Status (Read) 2 x 0 1 1 1 Scratchpad 1 0 0 0 0 Divisor Latch (Least Significant Byte) 1 0 0 0 1 Divisor Latch (Most Significant Byte) 1 0 0 1 0 Alternate Function 6 Submit Documentation Feedback Copyright © 2006–2013, Texas Instruments Incorporated Product Folder Links: NS16C2552 NS16C2752 |
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