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LP8860-Q1 Datasheet(PDF) 22 Page - Texas Instruments |
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LP8860-Q1 Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 110 page  +1LSB PWM value 510 (10-bit) PWM value 510 ½ (10-bit) PWM value 511 (10-bit) 22 LP8860-Q1 SNVSA21F – MAY 2014 – REVISED JULY 2017 www.ti.com Product Folder Links: LP8860-Q1 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Table 3. GEN_DIV Coefficients and Resolution (continued) PWM_RESOLUTION[1:0] 00 01 10 11 PWM_ FREQ[3:0] STEP GEN_DIV RES (bits) STEP GEN_DIV RES (bits) STEP GEN_DIV RES (bits) STEP GEN_DIV RES (bits) 0111 304 215.58 7 152 431.16 8 76 862.32 9 38 1724.63 10 1000 320 204.80 7 160 409.60 8 80 819.20 9 40 1638.40 10 1001 336 195.05 7 168 390.10 8 84 780.19 9 42 1560.38 10 1010 352 186.18 7 176 372.36 8 88 744.73 9 44 1489.45 10 1011 368 178.09 7 184 356.17 8 92 712.35 9 46 1424.70 10 1100 384 170.67 7 192 341.33 8 96 682.67 9 48 1365.33 10 1101 400 163.84 7 200 327.68 8 100 655.36 9 50 1310.72 10 1110 448 146.29 7 224 292.57 8 112 585.14 9 56 1170.29 10 1111 512 128.00 7 256 256.00 8 128 512.00 9 64 1024.00 10 Dithering allows increased resolution and smaller average steps size. Dithering can be programmed with EEPROM bits <DITHER[2:0]> 0 to 4 bits. Figure 13 shows 1-bit dithering. For 3-bit dithering, every 8th pulse is made 1 LSB longer to increase the average value by 1/8th. Dither is available in steady state condition when <EN_STEADY_DITHER> is high, otherwise during slope only. Figure 13. Example of the Dithering, 1-Bit Dither, 10-Bit Resolution 8.3.2 Brightness Control (Display Mode) The LP8860-Q1 LED outputs can be configured to display or cluster mode. The following sections describe display mode options. Cluster mode is a special mode with individually controlled LED outputs. See Cluster Mode section for details. The LP8860-Q1 controls the brightness of the display with conventional PWM or with Hybrid PWM and Current dimming. Brightness control is received either from PWM input pin or from I2C/SPI register bits. The brightness source is selected with <BRT_MODE[1:0]> bits as follows: Table 4. Brightness Control Selection BRT_MODE[1:0] BRIGHTNESS CONTROL 00 PWM input duty cycle 01 PWM input duty cycle x Brightness register 10 Brightness register 11 PWM direct control (PWM in = PWM out) 8.3.2.1 PWM Input Duty Cycle Based Control In this mode the LED brightness is controlled by the input PWM duty cycle. The PWM detector block measures the duty cycle in the PWM pin and uses this 16-bit value to control the duty cycle of the LED output PWM. Input PWM period is measured from rising edge to the next rising edge. The ratio of input PWM frequency and 10-MHz sampling clock defines resolution reachable with external PWM. PWM input block timeout is 24 ms after the last rising edge; it must be taken into account for 0% and 100% brightness setting. For setting 100% brightness, a high-level PWM input signal must last at least 24 ms. The minimum on and off time for the PWM input signal is 400 ns. |
Similar Part No. - LP8860-Q1_17 |
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Similar Description - LP8860-Q1_17 |
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