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GS12181 Datasheet(PDF) 21 Page - Semtech Corporation |
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GS12181 Datasheet(HTML) 21 Page - Semtech Corporation |
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21 / 68 page  GS12181 Final Data Sheet Rev.5 PDS-060905 October 2016 21 of 68 Semtech Proprietary & Confidential www.semtech.com 4.3 Output Cable Drivers The GS12181 features two independent internally terminated differential cable drivers (see Figure 3-2), with data available on the first output, SDO0, while clock and data are available on the second output, SDO1. Although SDO0 and SDO1 are differential buffers, they can be implemented as 4 SMPTE compliant 75Ω single-ended drivers. However, if the inverted signal on SDO0 and SDO1 are not used, those outputs should be terminated through a 75Ω resistor and 4.7μF capacitor to GND. The cable drivers feature highly configurable amplitude and pre-emphasis control, which can compensate for up to 8 inches of 10mil microstrip in standard FR4 at 11.88Gb/s. The LOS (Loss of Signal) status from the input stage and Loss of Lock status from the CDR block can both be used to automatically mute or disable the outputs when asserted. 4.3.1 Bypassed Re-timer Signal Output Control With the default power-up settings, the GS12181 outputs will automatically switch to the bypassed signal (non-re-timed) whenever the PLL is unlocked. Alternatively, manual re-timer bypass may be configured by setting the CTRL_OUTPUT<n>_RETIMER_ AUTO_BYPASS and CTRL_OUTPUT<n>_RETIMER_MANUAL_BYPASS parameters in register 0x734C to 0b and 1b respectively, in which case the PLL will remain bypassed for all rates. 0x730C 12:8 CFG_PLL_LBW_SD Set the LBW for SD signals. 4:0 CFG_PLL_LBW_MADI Set the LBW for MADI signals. 0x7311 8:8 CFG_GPIO1_OUTPUT_ ENA Sets the GPIO pin as either an output or an input. 7:0 CFG_GPIO1_FUNCTION Sets or disables buffered reference clock output on GPIO1. Table 4-5: CDR Control Parameters (Continued) Addressh Bit Slice Parameter Name Description Table 4-6: CDR Status Parameters Addressh Bit Slice Parameter Name Description 0x7385 15:8 STAT_CNT_RATE_CHANGES Counter showing the number of times the PLL lock rate changed. 7:0 STAT_CNT_PLL_LOCK_CHANGES Counter showing the number of times the PLL lock status changed. 0x7386 12:12 STAT_LOCK The status of the PLL. Locked, or unlocked. 0x7387 2:0 STAT_DETECTED_RATE The rate at which the PLL is locked to. |
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