Electronic Components Datasheet Search |
|
DAC38RF80_017 Datasheet(PDF) 51 Page - Texas Instruments |
|
DAC38RF80_017 Datasheet(HTML) 51 Page - Texas Instruments |
51 / 155 page 51 DAC38RF80, DAC38RF83, DAC38RF84 DAC38RF85, DAC38RF90, DAC38RF93 www.ti.com SLASEA3C – DECEMBER 2016 – REVISED JULY 2017 DAC38RF83 DAC38RF93 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated program that particular DAC chip to use phase tolerance window “00”. This mapping is indicated in the figure with the label “θ1|θ12|θ2: window=00”. Having programmed the device to use window “00”, all future SYSREF events that occur in θ1 or θ2 would trigger the LMFC and frame clock to be aligned using the following rising clock edge as the alignment reference (as indicated by the red arrow pointing to rising clock edge “R” and labeled “Window=00/01 alignment edge”). The full extent of each phase tolerance window is indicated in the figure using “box and whisker” plots. For the “window=00” example, the “box” portion of the plot indicates that the phase tolerance window is centered on θ12 (to be precise on the boundary between θ1 and θ2) and the “whisker” portion indicates that even if the rising edge of SYSREF occurs as early as the preceding θ4 or as late as the following θ3 it still results in LMFC and frame clock alignment to the same rising clock edge indicated by the red arrow labeled “Window=00/01 alignment edge”. When programmed for phase tolerance window “00”, the DAC chip is tolerant to variations in the SYSREF timing ranging from a rising SYSREF edge that occurs just after one rising edge of clock to just before the next rising edge of the clock. The qualifying phrases “just after” and “just before” are used here to indicate that the SYSREF transition must occur far enough away from the rising edges of the clock to avoid setup/hold violations and prevent the device from concluding that the SYSREF transition has crossed out off the phase tolerance window when in fact it has not. The tolerance range for window “00” is from rising clock edge to rising clock edge and is indicated in the figure by the green text labeled “tolerance = R ↔R”. Following the above example, if characterization reveals SYSREF timing centered on θ23 then phase tolerance window “01” (with tolerance for SYSREF rising edge events from EF to EF) should be chosen. Notice that this option is tolerant even to rising SYSREF edges that occur after the rising device clock edge (i.e. in θ4) and will treat them just as if they had occurred in one of the earlier three phases, aligning to the same rising device clock edge indicated by the red arrow labeled “Window=00/01 Alignment Edge”. This allows the system designer to tolerate PCB design errors and/or environmental and manufacturing variations – achieving his intended alignment without having to make physical changes to the board to adjust the SYSREF timing. Similarly, if characterization indicates that SYSREF timing is centered on θ34 or θ41 then phase tolerance window “10” or “11” can be selected, resulting in tolerance for “F ↔F” or “ER↔ER” SYSREF timing, respectively. Note, however, that in these two cases the alignment reference edge is by default taken to be the subsequent rising edge of the device clock. Since this may not be the desired behavior, the DAC38RFxx allows the user to program in an optional alignment offset of θ1 if the default offset of 0 does not achieve the desired alignment. This feature is illustrated in Figure 56 where the user can see that by setting the alignment offset to -1, phase tolerance windows “10” and “11” can be made to trigger alignment to the earlier rising device clock edge used by windows “00” and “01”. Alternatively, the window “00” and “01” alignment edge can be pushed one cycle later by setting their alignment offset to +1. Figure 56. Optional SYSREF Alignment Offset |
Similar Part No. - DAC38RF80_017 |
|
Similar Description - DAC38RF80_017 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.COM |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Datasheet Upload | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |