ADS114S08BIPBS datasheet(7/88 Pages) TI1

Part #	ADS114S08BIPBS

Description	Low-Power, Low-Noise, Highly Integrated, 6- and 12-Channel, 4-kSPS, 16-Bit, Delta-Sigma ADC With PGA and Voltage Reference

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ADS114S06B, ADS114S08B

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SBAS852 – AUGUST 2017

Product Folder Links: ADS114S06B ADS114S08B

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(1)

Excluding error of voltage reference.

(2)

See the 50-Hz and 60-Hz Line Cycle Rejection section for more information.

7.5 Electrical Characteristics

minimum and maximum specifications apply from TA = –40°C to +125°C; typical specifications are at TA = 25°C;

all specifications are at AVDD = 2.7 V to 5.25 V, AVSS = 0 V, DVDD = IOVDD = 3.3 V, all gains, internal reference, internal

oscillator, and all data rates (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

ANALOG INPUTS

Absolute input current

PGA bypassed,

AVSS + 0.1 V

≤ V(AINx) ≤ AVDD – 0.1 V

±0.5

nA

PGA enabled, gain 1 to 128,

V(AINx)MIN ≤ V(AINx) ≤ V(AINx)MAX

–10

±0.1

10

Differential input current

PGA bypassed,

VCM = AVDD / 2, –VREF ≤ VIN ≤ VREF

±1

nA/V

PGA enabled, gain 1 to 128,

VCM = AVDD / 2, –VREF / Gain ≤ VIN ≤ VREF / Gain

±0.02

nA

PGA

Gain settings

1, 2, 4, 8, 16,

32, 64, 128

Startup time

Enabling the PGA in conversion mode

190

µs

SYSTEM PERFORMANCE

Resolution (no missing codes)

16

Bits

DR

Data rate

2.5, 5, 10, 16.6,

20, 50, 60, 100,

200, 400, 800,

1000, 2000, 4000

SPS

INL

Integral nonlinearity (best fit)

PGA bypassed, VCM = AVDD / 2

1

ppmFSR

PGA enabled, gain = 1 to 128, VCM = AVDD / 2

2

25

VIO

Input offset voltage

PGA bypassed

20

µV

PGA enabled, gain = 1 to 8

20 / Gain

PGA enabled, gain = 16 to 128

2

PGA bypassed, after internal offset calibration

On the order of noisePP at the

set DR and gain

PGA enabled, gain = 1 to 128, after internal offset

calibration

On the order of noisePP at the

set DR and gain

Offset drift

PGA bypassed

10

nV/°C

PGA enabled, gain = 1 to 128

15

Gain error(1)

TA = 25°C, PGA bypassed

0.01%

0.1%

TA = 25°C, PGA enabled, gain = 1 to 128

0.025%

0.2%

Gain drift(1)

PGA bypassed

0.5

ppm/°C

PGA enabled, gain = 1 to 128

1

Noise (input-referred)

See the Noise Performance section

NMRR

Normal-mode rejection ratio(2)

fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS

75

95

dB

fIN = 50 Hz or 60 Hz (±1 Hz), DR = 20 SPS,

external fCLK = 4.096 MHz

95

CMRR

Common-mode rejection ratio

At dc

120

dB

fCM = 50 Hz or 60 Hz (±1 Hz),

DR = 2.5 SPS, 5 SPS, 10 SPS, 20 SPS

125

PSRR

Power-supply rejection ratio

AVDD at dc

105

dB

AVDD at 50 Hz or 60 Hz

115

DVDD at dc

115

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