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PC87372 Datasheet(PDF) 6 Page - National Semiconductor (TI) |
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PC87372 Datasheet(HTML) 6 Page - National Semiconductor (TI) |
6 / 144 page Table of Contents (Continued) 6 www.national.com Revision 1.2 3.3 MODULE CONTROL ................................................................................................................. 36 3.3.1 Module Enable/Disable ................................................................................................ 36 3.3.2 Floating Module Output ............................................................................................... 37 3.4 INTERNAL ADDRESS DECODING .......................................................................................... 37 3.5 PROTECTION ........................................................................................................................... 38 3.5.1 Multiplexed Pins Configuration Lock ........................................................................... 38 3.5.2 GPIO Ports Configuration Lock ................................................................................... 38 3.5.3 Fast Disable Configuration Lock .................................................................................. 38 3.5.4 Clock Control Lock ...................................................................................................... 38 3.5.5 GPIO Ports Lock .......................................................................................................... 38 3.5.6 Fan Speed Configuration Lock .................................................................................... 38 3.5.7 SWC Configuration Lock ............................................................................................. 38 3.6 REGISTER TYPE ABBREVIATIONS ........................................................................................ 39 3.7 PC87372 CONFIGURATION REGISTERS ............................................................................... 39 3.7.1 SuperI/O ID Register (SID) .......................................................................................... 39 3.7.2 SuperI/O Configuration 1 Register (SIOCF1) .............................................................. 40 3.7.3 SuperI/O Configuration 2 Register (SIOCF2) .............................................................. 41 3.7.4 SuperI/O Configuration 6 Register (SIOCF6) .............................................................. 41 3.7.5 SuperI/O Revision ID Register (SRID) ........................................................................ 42 3.7.6 Clock Generator Control Register (CLOCKCF) ........................................................... 42 3.8 FLOPPY DISK CONTROLLER (FDC) CONFIGURATION ........................................................ 44 3.8.1 General Description ..................................................................................................... 44 3.8.2 Logical Device 0 (FDC) Configuration ......................................................................... 44 3.8.3 FDC Configuration Register ........................................................................................ 45 3.8.4 Drive ID Register ......................................................................................................... 46 3.9 PARALLEL PORT (PP) CONFIGURATION .............................................................................. 47 3.9.1 General Description ..................................................................................................... 47 3.9.2 Logical Device 1 (PP) Configuration ............................................................................ 47 3.9.3 Parallel Port Standard Configuration Register ............................................................. 48 3.9.4 Parallel Port Modified Configuration Register .............................................................. 49 3.10 SERIAL PORT CONFIGURATION ............................................................................................ 50 3.10.1 General Description ..................................................................................................... 50 3.10.2 Logical Device 3 (SP) Configuration ............................................................................ 50 3.10.3 Serial Port Configuration Register ............................................................................... 51 3.11 SYSTEM WAKE-UP CONTROL (SWC) CONFIGURATION ..................................................... 52 3.11.1 General Description ..................................................................................................... 52 3.11.2 Logical Device 4 (SWC) Configuration ........................................................................ 52 3.12 KEYBOARD AND MOUSE CONTROLLER (KBC) CONFIGURATION ..................................... 53 3.12.1 General Description ..................................................................................................... 53 3.12.2 Logical Devices 5 and 6 (Mouse and Keyboard) Configuration .................................. 53 3.12.3 KBC Configuration Register ........................................................................................ 54 3.13 GENERAL-PURPOSE INPUT/OUTPUT (GPIO) PORTS CONFIGURATION .......................... 55 3.13.1 General Description ..................................................................................................... 55 3.13.2 Logical Device 7 (GPIO) Configuration ....................................................................... 56 3.13.3 GPIO Pin Select Register (GPSEL) ............................................................................. 57 |
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