 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
MAX1190 Datasheet(PDF) 5 Page - Maxim Integrated Products |
|
||||||||||||||||||||||||||||||
MAX1190 Datasheet(HTML) 5 Page - Maxim Integrated Products |
|
|
5 / 21 page 
Dual 10-Bit, 120Msps, 3.3V, Low-Power ADC with Internal Reference and Parallel Outputs _______________________________________________________________________________________ 5 Note 1: Intermodulation distortion is the total power of the intermodulation products relative to the total input power. Note 2: REFP, REFN, and COM should be bypassed to GND with a 0.1µF (min) or 1µF (typ) capacitor. Note 3: Digital outputs settle to VIH, VIL. Parameter guaranteed by design. Note 4: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down. Note 5: Amplitude matching is measured by applying the same signal to each channel and comparing the magnitude of the funda- mental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test. Note 6: Phase matching is measured by applying the same signal to each channel and comparing the phase of the fundamental of the calculated FFT. The data from both ADC channels must be captured simultaneously during this test. PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating, fINA and B = 20.01MHz at -0.5dB FS 149 185 Sleep mode 3 mA Analog Supply Current IVDD Shutdown, clock idle, PD = OE = OVDD 115 µA Operating, fINA and B = 20.01MHz at -0.5dB FS; see Typical Operating Characteristics section, Digital Supply Current vs. Analog Input Frequency 16 mA Sleep mode 100 Output Supply Current IOVDD Shutdown, clock idle, PD = OE = OVDD 210 µA Operating, fINA and B = 20.01MHz at -0.5dB FS 492 611 mW Sleep mode 10 mW Analog Power Dissipation PDISS Shutdown, clock idle, PD = OE = OVDD 3.3 50 µW Offset, VDD ±5% ±3.4 mV/V Power-Supply Rejection Ratio PSRR Gain, VDD ±5% ±0.81 %/V TIMING CHARACTERISTICS CLK Rise to Output Data Valid Time tDO CL = 20pF (Note 3) 4.8 7.4 ns OE Fall to Output Enable Time tENABLE 4.7 ns OE Rise to Output Disable Time tDISABLE 1.2 ns CLK Pulse Width High tCH Clock period: 8.34ns; see Typical Operating Characteristics section, AC Performance vs. Clock Duty Cycle 4.17 ns CLK Pulse Width Low tCL Clock period: 8.34ns; see Typical Operating Characteristics section, AC Performance vs. Clock Duty Cycle 4.17 ns Wake up from sleep mode (Note 4) 0.65 Wake-Up Time tWAKE Wake up from shutdown mode (Note 4) 1.2 µs CHANNEL-TO-CHANNEL MATCHING Crosstalk fINA or B = 20.01MHz at -0.5dB FS -71 dBc Gain Matching fINA or B = 20.01MHz at -0.5dB FS (Note 5) 0.08 ±0.2 dB Phase Matching fINA or B = 20.01MHz at -0.5dB FS (Note 6) 0.8 Degrees ELECTRICAL CHARACTERISTICS (continued) (VDD = 3.3V; OVDD = 2V; 0.1µF and 1.0µF capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a 10k Ω resistor; VREFIN = 2.048V; VIN = 2VP-P (differential with respect to COM); CL = 10pF at digital outputs; fCLK = 120MHz; TA = TMIN to TMAX, unless otherwise noted; ≥+25°C guaranteed by production test, <+25°C guaranteed by design and characterization; typical values are at TA = +25°C.) |
English ▼
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
