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SN75C23243CDLR Datasheet(PDF) 7 Page - Texas Instruments |
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SN75C23243CDLR Datasheet(HTML) 7 Page - Texas Instruments |
7 / 19 page SN65C23243, SN75C23243 3V TO 5.5V DUAL RS232 PORT SLLS513A − AUGUST 2001 − REVISED MARCH 2004 7 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RECEIVER SECTION electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 7) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT VOH High-level output voltage IOH = −1 mA VCC − 0.6 V VCC − 0.1 V V VOL Low-level output voltage IOL = 1.6 mA 0.4 V VIT+ Positive-going input threshold voltage VCC = 3.3 V 1.6 2.4 V VIT+ Positive-going input threshold voltage VCC = 5 V 1.9 2.4 V VIT− Negative-going input threshold voltage VCC = 3.3 V 0.6 1.1 V VIT− Negative-going input threshold voltage VCC = 5 V 0.8 1.4 V Vhys Input hysteresis (VIT+ − VIT−) 0.5 V Ioff Output leakage current (except ROUT2B) FORCEOFF = 0 V ±0.05 ±10 µA ri Input resistance VI = ±3 V to ±25 V 3 5 7 k Ω † All typical values are at VCC = 3.3 V or VCC = 5 V and TA = 25°C. NOTE 4: Test conditions are C1−C4 = 0.22 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V. switching characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Note 4 and Figure 7) PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT tPLH Propagation delay time, low- to high-level output CL = 150 pF, See Figure 4 150 ns tPHL Propagation delay time, high- to low-level output CL = 150 pF, See Figure 4 150 ns ten Output enable time CL = 150 pF, RL = 3 kΩ See Figure 5 200 ns tdis Output disable time CL = 150 pF, RL = 3 kΩ, See Figure 5 200 ns tsk(p) Pulse skew‡ See Figure 4 50 ns † All typical values are at VCC = 3.3 V or VCC = 5 V and TA = 25°C. ‡ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device. NOTE 4: Test conditions are C1−C4 = 0.22 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V. |
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