RS5C372A-E2-F datasheet(54/57 Pages) RICOH

Part #	RS5C372A-E2-F

Description	I2C bus SERIAL INTERFACE REAL-TIME CLOCK IC

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Manufacturer	RICOH [RICOH electronics devices division]

Direct Link	http://www.ricoh.com

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54 / 57 page

RS5C372A/B

53

7.3 Read Operation from Clock and Calendar Counters

Stop condition

Start condition

Read from clock and

calendar counters

*1

*2

1) When reading from clock and calendar counters, do

not insert stop condition until all times from second to

year have been read to prevent error in reading time.

2) Take care so that process from start condition to stop

condition will be completed within 0.5 seconds. (The

RS5C372A/B force access to the CPU to terminate

within 0.5 to 1.0 seconds after start condition has

occurred in case the CPU is failed during access.)

7.4 Second Digit Adjustment by

30 seconds

Control register 2←(00

×1×111) *1

1) Write 1 to the ADJ bit. (The 30 seconds of

adjustment is made within 122.1

s (125s when

32.000kHz crystal is used) after the ADJ bit is set

to 1.)

7.5 Interrupt Operation

7.5-1 Periodic Interrupt Operation

CTFG=1?

Periodic interrupt operation

Other

interrupt

operation

Interrupt to CPU

Control register 2←(00

×××011)

Set periodic interrupt

cycle select bit and

interrupt output select bit

YES

NO

*1

*2

*1) The level mode is used for the periodic interrupt

cycle select bit.

*2) Interrupt to the CPU is cancelled by setting the

CTFG bit to 0.

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RS5C372A-E2-F Datasheet(PDF) 54 Page - RICOH electronics devices division

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