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MSP430FR2111IRLLR Datasheet(PDF) 12 Page - Texas Instruments |
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MSP430FR2111IRLLR Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 78 page  12 MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000 SLASE78B – AUGUST 2016 – REVISED JULY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000 Terminal Configuration and Functions Copyright © 2016–2017, Texas Instruments Incorporated (1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the Px.0 to Px.7 unused pin connection guidelines. (2) The pulldown capacitor should not exceed 1.1 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode with TI tools like FET interfaces or GANG programmers. 4.4 Pin Multiplexing Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For details of the settings for each pin and schematics of the multiplexed ports, see Section 6.11.15. 4.5 Connection of Unused Pins Table 4-3 lists the correct termination of unused pins. Table 4-3. Connection of Unused Pins(1) PIN POTENTIAL COMMENT Px.0 to Px.7 Open Set to port function, output direction (PxDIR.n = 1) RST/NMI DVCC 47-k Ω pullup or internal pullup selected with 10-nF (1.1 nF) pulldown(2) TEST Open This pin always has an internal pulldown enabled. (1) Only for input pins 4.6 Buffer Type Table 4-4 defines the pin buffer types that are listed in Table 4-1. Table 4-4. Buffer Type BUFFER TYPE (STANDARD) NOMINAL VOLTAGE HYSTERESIS PU OR PD NOMINAL PU OR PD STRENGTH (µA) OUTPUT DRIVE STRENGTH (mA) OTHER CHARACTERISTICS LVCMOS 3.0 V Y(1) Programmable See Section 5.13.4. See Section 5.13.4.1. Analog 3.0 V No No N/A N/A See the analog modules in Section 5 for details. Power (DVCC) 3.0 V No No N/A N/A SVS enables hysteresis on DVCC. Power (AVCC) 3.0 V No No N/A N/A |
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