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MSP430FR2111IRLLR Datasheet(PDF) 22 Page - Texas Instruments |
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MSP430FR2111IRLLR Datasheet(HTML) 22 Page - Texas Instruments |
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22 / 78 page  22 MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000 SLASE78B – AUGUST 2016 – REVISED JULY 2017 www.ti.com Submit Documentation Feedback Product Folder Links: MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000 Specifications Copyright © 2016–2017, Texas Instruments Incorporated Table 5-7 lists the characteristics of the VLO. (1) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C)) (2) Calculated using the box method: (MAX(1.8 V to 3.6 V) – MIN(1.8 V to 3.6 V)) / MIN(1.8 V to 3.6 V) / (3.6 V – 1.8 V) Table 5-7. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fVLO VLO frequency Measured at MCLK 3.0 V 10 kHz dfVLO/dT VLO frequency temperature drift Measured at MCLK(1) 3.0 V 0.5 %/°C dfVLO/dVCC VLO frequency supply voltage drift Measured at MCLK(2) 1.8 V to 3.6 V 4 %/V f Duty cycle Measured at MCLK 3.0 V 50% NOTE The VLO clock frequency is reduced by 15% (typical) when the device switches from active mode to LPM3 or LPM4, because the reference changes. This lower frequency is not a violation of the VLO specifications (see Table 5-7). Table 5-8 lists the characteristics of the MODOSC. Table 5-8. Module Oscillator (MODOSC) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fMODOSC MODOSC frequency 3.0 V 3.8 4.8 5.8 MHz fMODOSC/dT MODOSC frequency temperature drift 3.0 V 0.102 %/°C fMODOSC/dVCC MODOSC frequency supply voltage drift 1.8 V to 3.6 V 2.29 %/V fMODOSC,DC Duty cycle 3.0 V 40% 50% 60% 5.13.4 Digital I/Os Table 5-9 lists the characteristics of the digital inputs. (1) The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted. (2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Table 5-9. Digital Inputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VIT+ Positive-going input threshold voltage 2 V 0.90 1.50 V 3 V 1.35 2.25 VIT– Negative-going input threshold voltage 2 V 0.50 1.10 V 3 V 0.75 1.65 Vhys Input voltage hysteresis (VIT+ – VIT–) 2 V 0.3 0.8 V 3 V 0.4 1.2 RPull Pullup or pulldown resistor For pullup: VIN = VSS For pulldown: VIN = VCC 20 35 50 kΩ CI,dig Input capacitance, digital only port pins VIN = VSS or VCC 3 pF CI,ana Input capacitance, port pins with shared analog functions VIN = VSS or VCC 5 pF Ilkg(Px.y) High-impedance leakage current(1)(2) 2 V, 3 V –20 +20 nA |
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