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MSP430FR2111IRLLR Datasheet(PDF) 17 Page - Texas Instruments

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Part No. MSP430FR2111IRLLR
Description  Mixed-Signal Microcontrollers
Download  78 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

MSP430FR2111IRLLR Datasheet(HTML) 17 Page - Texas Instruments

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VBOR
VSVS–
VSVS+
t
V
Power Cycle Reset
SVS Reset
BOR Reset
tBOR
17
MSP430FR2111, MSP430FR2110, MSP430FR2100, MSP430FR2000
www.ti.com
SLASE78B – AUGUST 2016 – REVISED JULY 2017
Submit Documentation Feedback
Product Folder Links: MSP430FR2111 MSP430FR2110 MSP430FR2100 MSP430FR2000
Specifications
Copyright © 2016–2017, Texas Instruments Incorporated
(1)
For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2)
These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a
JEDEC-defined 1S0P system) and will change based on environment and application. For more information, see these EIA/JEDEC
standards:
JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air)
JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements
5.12 Thermal Resistance Characteristics
THERMAL METRIC(1) (2)
VALUE
UNIT
JA
Junction-to-ambient thermal resistance, still air
VQFN 24 pin (RLL)
38.7
ºC/W
TSSOP 16 pin (PW16)
106.5
JC
Junction-to-case (top) thermal resistance
VQFN 24 pin (RLL)
39.5
ºC/W
TSSOP 16 pin (PW16)
41.2
JB
Junction-to-board thermal resistance
VQFN 24 pin (RLL)
8.6
ºC/W
TSSOP 16 pin (PW16)
51.5
5.13 Timing and Switching Characteristics
5.13.1 Power Supply Sequencing
Figure 5-4 shows the power cycle, SVS, and BOR reset conditions.
Figure 5-4. Power Cycle, SVS, and BOR Reset Conditions
Table 5-1 lists the characteristics of the SVS and BOR.
(1)
A safe BOR can only be correctly generated only if DVCC must drop below this voltage before it rises.
(2)
When an BOR occurs, a safe BOR can be correctly generated only if DVCC is kept low longer than this period before it reaches VSVSH+.
Table 5-1. PMM, SVS and BOR
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VBOR, safe
Safe BOR power-down level(1)
0.1
V
tBOR, safe
Safe BOR reset delay(2)
10
ms
ISVSH,AM
SVSH current consumption, active mode
VCC = 3.6 V
1.5
µA
ISVSH,LPM
SVSH current consumption, low-power modes
VCC = 3.6 V
240
nA
VSVSH-
SVSH power-down level
1.71
1.81
1.86
V
VSVSH+
SVSH power-up level
1.74
1.88
1.99
V
VSVSH_hys
SVSH hysteresis
80
mV
tPD,SVSH, AM
SVSH propagation delay, active mode
10
µs
tPD,SVSH, LPM
SVSH propagation delay, low-power modes
100
µs


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