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ICS93716 Datasheet(PDF) 6 Page - Integrated Circuit Systems |
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ICS93716 Datasheet(HTML) 6 Page - Integrated Circuit Systems |
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6 ICS93716 0420E—04/01/03 Notes: 1. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. Timing Requirements TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120Ω, CL=15pF (unless otherwise PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Max clock frequency 3 freqop 33 233 MHz Application Frequency Range 3 freqApp 60 170 MHz Input clock duty cycle dtin 40 60 % CLK stabilization TSTAB 100 µs Switching Characteristics TA = 0 - 85C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V, RL = 120Ω, CL=15pF (unless otherwise stated) PARAMETER SYMBOL CONDITION MIN TYP MAX UNITS Low-to high level propagation delay time tPLH 1 CLK_IN to any output 5.5 ns High-to low level propagation delay time tPHL 1 CLK_IN to any output 5.5 ns Duty Cycle DC 49 51 % Input clock slew rate tsl(I) 14 v/ns Cycle to Cycle Jitter 1 tcyc-tcyc 66/100/125/133/167MHz 75 ps Phase error t(phase error) 4 -150 0 50 ps Output to Output Skew tskew 75 100 ps Rise Time, Fall Time tr, tf See figure 8 650 950 ps |
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