Receiver Switching Characteristics

Over recommended operating supply and temperature ranges unless otherwise specified

Symbol

Parameter

Min

Typ

Max

Units

CLHT

CMOS/TTL Low-to-High Transition Time (

Figure 2)

2

3.5

ns

CHLT

CMOS/TTL High-to-Low Transition Time (

Figure 2)

1.8

3.5

ns

RSPos0

Receiver Input Strobe Position for Bit 0 (

Figure 8)

f = 75 MHz

0.58

0.95

1.32

ns

RSPos1

Receiver Input Strobe Position for Bit 1

2.49

2.86

3.23

ns

RSPos2

Receiver Input Strobe Position for Bit 2

4.39

4.76

5.13

ns

RSPos3

Receiver Input Strobe Position for Bit 3

6.30

6.67

7.04

ns

RSPos4

Receiver Input Strobe Position for Bit 4

8.20

8.57

8.94

ns

RSPos5

Receiver Input Strobe Position for Bit 5

10.11

10.48

10.85

ns

RSPos6

Receiver Input Strobe Position for Bit 6

12.01

12.38

12.75

ns

RSKM

Receiver Skew Margin (when used with DS90CR287) (Note

4) (

Figure 9)

f = 75 MHz

380

ps

RCOP

RxCLK OUT Period (

Figure 3)

13.33

T

50

ns

RCOH

RxCLK OUT High Time (

Figure 3)

f = 75 MHz

3.6

5

6.0

ns

RCOL

RxCLK OUT Low Time (

Figure 3)

3.6

5

6.0

ns

RSRC

RxOUT Setup to RxCLK OUT (

Figure 3)

3.5

ns

RHRC

RxOUT Hold to RxCLK OUT (

Figure 3)

3.5

ns

RCCD

3.4

5.0

7.3

ns

RPLLS

Receiver Phase Lock Loop Set (

Figure 5)10

ms

RPDD

Receiver Powerdown Delay (

Figure 7)1

µs

Note 4: Receiver Skew Margin is defined as the valid data sampling region at the receiver inputs. This margin takes into account the transmitter pulse positions (min

and max) and the receiver input setup and hold time (internal data sampling window-RSPOS). This margin allows LVDS interconnect skew, inter-symbol interference

(both dependent on type/length of cable), and source clock (less than 250 ps).

Note 5: Total latency for the channel link chipset is a function of clock period and gate delays through the transmitter (TCCD) and receiver (RCCD). The total latency

for the 217/287 transmitter and 218/288 receiver is: (T + TCCD) + (2*T + RCCD), where T = Clock period. See also DS90CR287/DS90CR288A datasheet.

AC Timing Diagrams

DS100872-2

FIGURE 1. “Worst Case” Test Pattern

DS100872-5

DS100872-6

FIGURE 2. DS90CR288 (Receiver) CMOS/TTL Output Load and Transition Times

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