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DS28E04-100 Datasheet(PDF) 10 Page - Dallas Semiconductor |
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DS28E04-100 Datasheet(HTML) 10 Page - Dallas Semiconductor |
10 / 36 page DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO 10 of 36 PIO Activity Latch State Register ADDR b7 b6 b5 b4 b3 b2 b1 b0 0222h 0 0 0 0 0 0 AL1 AL0 The data in this register represents the current state of the PIO activity latches. This register is read using the Read Memory command. This register is read-only. Each bit is associated with the activity latch of the respective PIO channel. Bits 2 to 7 have no function; they always read 0. A state transition on a PIO pin, High èLow or Low èHigh, of a duration greater than tPWMIN causes the associated bit in the register to be set to a 1. This register is cleared to 00h by a power-on reset, or by successful execution of the Reset Activity Latches command. The next three registers control the device's participation a Conditional Search ROM sequence. The interaction of the various signals that determine whether the device responds to a conditional search is illustrated in Figure 7. There is a selection mask, SM, to select the participating PIOs, a polarity selection SP to specify for each channel whether the channel signal needs to be 1 or 0 to qualify, and a PLS bit to select either the activity latches or PIO pins as inputs. The signals of all channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or OR’ed result as the conditional search response signal CSR. If CT is 0, the channel signal of at least one of the selected channels must match the corresponding polarity. If CT is 1, the channel signals of all selected channels must match the corresponding polarity. Figure 7. CONDITIONAL SEARCH LOGIC AL1 P1 PLS SP0 SM0 CT SM1 SP1 AL0 P0 CSR Channel 0 Channel 1 PORL Conditional Search Channel Selection Mask Register ADDR b7 b6 b5 b4 b3 b2 b1 b0 0223h 0 0 0 0 0 0 SM1 SM0 The data in this register controls whether a PIO channel qualifies for participation in the conditional search command. To include a PIO channel, the bits in this register that correspond to those channels need to be set to 1. This register can only be written through the Write Register command. This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7. Bits 2 to 7 have no function; they always read 0 and cannot be changed to 1. This register is cleared to 00h by a power-on reset. |
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