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ACPL-024L Datasheet(PDF) 11 Page - Broadcom Corporation. |
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ACPL-024L Datasheet(HTML) 11 Page - Broadcom Corporation. |
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11 / 16 page  Broadcom - 11 - ACPL-M21L, ACPL-021L, ACPL-024L, ACPL-W21L, ACPL-K24L Data Sheet Switching Specifications (AC) Over recommended temperature (TA = –40°C to +105°C), supply voltage (2.7V ≤ VDD ≤ 5.5V). All typical specifications are at VDD = 2.7V, TA = 25°C. NOTE Use of a 0.1 μF bypass capacitor connected between VDD and ground is recommended. Package Characteristics All typical at TA = 25°C. Table 8 Switching Specifications (AC) Parameter Symbol Min. Typ. Max. Units Test Conditions Propagation Delay Time to Logic Low Outputa a. tPHL propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% VDD of the falling edge of the VO signal. tPLH propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% level of the rising edge of the VO signal. tPHL 130 250 ns IF=2.2 mA, CL=15 pF (Figure 13, Figure 17), CMOS Signal Levels Propagation Delay Time to Logic High Outputa tPLH 115 250 ns IF=2.2 mA, CL=15 pF (Figure 14, Figure 17), CMOS Signal Levels Pulse Width Distortionb b. PWD is defined as |tPHL – tPLH|. PWD 200 ns CMOS Signal Levels Propagation Delay Skewc c. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the recommended operating conditions. tPSK 220 ns Output Rise Time (10% to 90%) tR 11 ns IF = 2.2 mA, CL= 15 pF, CMOS Signal Levels. Output Fall Time (90% to 10%) tF 11 ns IF = 2.2 mA, CL= 15 pF, CMOS Signal Levels. Static Common Mode Transient Immunity at Logic High Outputd d. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. |CMH|25 40 kV/μs VCM = 1000V, TA = 25°C, IF = 2.2 mA, CL= 15 pF, VI = 5V, (RT = 1.6 k) or VI = 3.3V, (RT = 840 ), CMOS Signal Levels, Figure 18 Static Common Mode Transient Immunity at Logic Low Outpute e. CML is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state. |CML|25 40 kV/μs VCM = 1000V, TA = 25°C, IF = 0 mA, CL= 15 pF, VI = 0V, (RT = 1.6 k) or (RT = 840), CMOS Signal Levels, Figure 18 Table 9 Package Characteristics Parameter Symbol Part Number Min. Typ. Max. Units Test Conditions Input-Output Insulation VISO ACPL-M21L/024L/021L 3750 Vrms RH < 50% for 1 min., TA = 25°C ACPL-W21L/K24L 5000 Input-Output Resistance RI-O 1012 VI-O = 500 V Input-Output Capacitance CI-O 0.6 pF f = 1 MHz, TA = 25°C |
Similar Part No. - ACPL-024L |
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Similar Description - ACPL-024L |
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