CPS-1848_17 datasheet(10/86 Pages) IDT

Part #	CPS-1848

Description	18-Port, 48-Lane, 240Gbps, Gen2 RapidIO Switch

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Manufacturer	IDT [Integrated Device Technology]

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June 26, 2017

CPS-1848 Datasheet

5.

Configuration Pins

Speed Select Pins SPD[2:0]

There are three port-speed selection pins that select the initial speed of the RapidIO ports (see Table 1). The RESET setting can be overridden by

programming the PLL n Control 1 Register and Lane n Control Register (for more information, see “Lane and Port Speeds” in the CPS-1848 User

Manual).

Quadrant Configuration Pins QCFG[7:0]

There are eight quadrant configuration selection pins, QCFG[7:0], or two pins per quadrant (see Figure 2). These pins configure the device’s

power-up settings for port width and lane to port mapping. After power-up these settings can be changed by updating the Quadrant Configuration

Register (for more information, see “Lane to Port Mapping” in the CPS-1848 User Manual).

Figure 2: Quadrant Configuration using QCFG[7:0]

Table 1: Port Speed Selection Pin Values

Value on the Pins

(SPD2, SPD1, SPD0)

Port Rate (Gbaud)

000

1.25

001

2.5

01X

5.0

100

Reserved

101

3.125

11X

6.25

Quadrant 1

Ports 1, 5, 9, 13, 17

QCFG[3:2]

Quadrant 0

Ports 0, 4, 8, 12, 16

QCFG[1:0]

Quadrant 3

Ports 3, 7, 11, 15

QCFG[7:6]

Quadrant 2

Ports 2, 6, 10, 14

QCFG[5:4]

Lanes 0-3

Lanes

16-19

Lanes

32-35

Lanes

36-39

Lanes

4-7

Lanes 28-31

Lanes 20-23

Lanes 8-11

Lanes

12-15

Lanes

44-47

Lanes

40-43

Lanes

24-27

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