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CPS-1432 Datasheet(PDF) 9 Page - Integrated Device Technology |
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CPS-1432 Datasheet(HTML) 9 Page - Integrated Device Technology |
9 / 79 page 9 ©2017 Integrated Device Technology, Inc. June 26, 2017 CPS-1432 Datasheet Rext (REXT_N/P) These pins establish the drive bias on the SerDes output. An external bias resistor is required. The two pins must be connected to one another with a 9.1k Ohm resistor. This provides robust SerDes stability across process and temperature. Speed Select (SPD[2:0]) These pins define the S-RIO port speed at RESET for all ports. SPD[2:0] can be configured as follows: • 000 = 1.25 Gbaud • 001 = 2.5 Gbaud • 01X = 5 Gbaud • 100 = Reserved • 101 = 3.125 Gbaud • 11X = 6.25 Gbaud For more information, see Speed Select Pins SPD[2:0]. Quadrant Config (QCFG[7:0]) These pins define the S-RIO port width (x1, x2, x4) at RESET for all ports. QCFG[1:0] defines port width for Quadrant 0, QCFG[3:2] defines port width for Quadrant 1, QCFG[5:4] defines port width for Quadrant 2, and QCFG[7:6] defines port width for Quadrant 3. For more information, see Quadrant Configuration Pins QCFG[7:0] . Frequency Select (FSEL[1:0]) FSEL1 pin defines the input reference clock, and FSEL0 pin defines the internal clock frequency, full or half rate. Multicast (MCAST) The Multicast-Event Control Symbol Trigger (MCAST) pin provides an optional mechanism to trigger the generation of a Multicast-Event Control Symbol. The multicast-event control symbol allows a user-defined system event to be multicast throughout a system (for example, synchronously reset a system or its internal timers). |
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