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9FGV0831 Datasheet(PDF) 1 Page - Integrated Device Technology

Part No. 9FGV0831
Description  8-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

9FGV0831 Datasheet(HTML) 1 Page - Integrated Device Technology

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DATASHEET
9FGV0831 JUNE 26, 2017
1
©2017 Integrated Device Technology, Inc.
8-Output Very Low-Power PCIe Gen 1-2-3-4
Clock Generator
9FGV0831
Description
The 9FGV0831 is a member of IDT's SOC-friendly 1.8V very
low-power PCIe clock family. The device has 8 output
enables for clock management, 2 different spread spectrum
levels in addition to spread off, and 2 selectable SMBus
addresses.
Recommended Application
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
8 100MHz Low-Power (LP) HCSL DIF pair
1 1.8V LVCMOS REF output with Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3-4 compliant
REF phase jitter is <1.5ps RMS
Features/Benefits
LP-HCSL outputs; saves 16 resistors compared to
standard PCIe devices
62mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 6 x 6 mm 48-VFQFPN; minimal board space
Block Diagram
XIN/CLKIN_25
X2
CONTROL
LOGIC
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SS Capable PLL
OSC
REF1.8
vOE(7:0)#
SCLK_3.3
vSADR
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
DIF6
DIF7


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