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9FGV0831 Datasheet(PDF) 3 Page - Integrated Device Technology

Part No. 9FGV0831
Description  8-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

9FGV0831 Datasheet(HTML) 3 Page - Integrated Device Technology

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JUNE 26, 2017
3
8-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
9FGV0831 DATASHEET
Pin Descriptions
PIN #
PIN NAME
TYPE
DESCRIPTION
1vSS_EN_tri
LATCHED
IN
Latched select input to select spread spectrum amount at initial power up :
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
2
GNDXTAL
GND
GND for XTAL
3
X1_25
IN
Crystal input, Nominally 25.00MHz.
4
X2
OUT
Crystal output.
5
VDDXTAL1.8
PWR
Power supply for XTAL, nominal 1.8V
6
VDDREF1.8
PWR
VDD for REF output. nominal 1.8V.
7vSADR/REF1.8
LATCHED
I/O
Latch to select SMBus Address/1.8V LVCMOS copy of X1/REFIN pin
8
GNDREF
GND
Ground pin for the REF outputs.
9
GNDDIG
GND
Ground pin for digital circuitry
10
SCLK_3.3
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
11
SDATA_3.3
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
12
VDDDIG1.8
PWR
1.8V digital power (dirty power)
13
VDDIO
PWR
Power supply for differential outputs
14
vOE0#
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
15
DIF0
OUT
Differential true clock output
16
DIF0#
OUT
Differential Complementary clock output
17
vOE1#
IN
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
18
DIF1
OUT
Differential true clock output
19
DIF1#
OUT
Differential Complementary clock output
20
VDD1.8
PWR
Power supply, nominal 1.8V
21
VDDIO
PWR
Power supply for differential outputs
22
GND
GND
Ground pin.
23
DIF2
OUT
Differential true clock output
24
DIF2#
OUT
Differential Complementary clock output
25
vOE2#
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
26
DIF3
OUT
Differential true clock output
27
DIF3#
OUT
Differential Complementary clock output
28
vOE3#
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
29
GNDA
GND
Ground pin for the PLL core.
30
VDDA1.8
PWR
1.8V power for the PLL core.
31
VDDIO
PWR
Power supply for differential outputs
32
DIF4
OUT
Differential true clock output
33
DIF4#
OUT
Differential Complementary clock output
34
vOE4#
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
35
DIF5
OUT
Differential true clock output
36
DIF5#
OUT
Differential Complementary clock output
37
vOE5#
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
38
VDD1.8
PWR
Power supply, nominal 1.8V
39
VDDIO
PWR
Power supply for differential outputs


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