9FGV0641AKLFT datasheet(6/16 Pages) IDT

Part #	9FGV0641AKLFT

Description	6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator with Zo=100ohms

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Manufacturer	IDT [Integrated Device Technology]

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6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR WITH ZO=100OHMS

6

JUNE 23, 2017

9FGV0641 DATASHEET

Electrical Characteristics–Input/Supply/Common Output Parameters–Normal

Operating Conditions

TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

Supply Voltage

VDDxx

Supply voltage for core, analog and single-ended

LVCMOS outputs

1.7

1.8

1.9

V

Output Supply Voltage

VDDIO

Supply voltage for differential Low Power Outputs

0.9975

1.05-1.8

1.9

V

Commercial range

0

25

70

°C

Industrial range

-40

25

85

°C

Input High Voltage

VIH

Single-ended inputs, except SMBus

0.75 VDD

VDD + 0.3

V

Input Mid Voltage

VIM

Single-ended tri-level inputs ('_tri' suffix)

0.4 VDD

0.5 VDD

0.6 VDD

V

Input Low Voltage

VIL

Single-ended inputs, except SMBus

-0.3

0.25 VDD

V

Output High Voltage

VIH

Single-ended outputs, except SMBus. IOH = -2mA

VDD-0.45

V

Output Low Voltage

VIL

Single-ended outputs, except SMBus. IOL = -2mA

0.45

V

IIN

Single-ended inputs, VIN = GND, VIN = VDD

-5

5

uA

IINP

Single-ended inputs

VIN = 0 V; Inputs with internal pull-up resistors

VIN = VDD; Inputs with internal pull-down resistors

-200

200

uA

Input Frequency

Fin

XTAL, or X1 input

23

25

27

MHz

Pin Inductance

Lpin

7nH

1

CIN

Logic Inputs, except DIF_IN

1.5

5

pF

1

COUT

Output pin capacitance

6

pF

1

Clk Stabilization

TSTAB

From VDD Power-Up and after input clock

stabilization or de-assertion of PD# to 1st clock

0.6

1.8

ms

1,2

SS Modulation Frequency

fMOD

Allowable Frequency

(Triangular Modulation)

30

31.6

33

kHz

1

OE# Latency

tLATOE#

DIF start after OE# assertion

DIF stop after OE# deassertion

1

3

clocks

1,3

Tdrive_PD#

tDRVPD

DIF output enable after

PD# de-assertion

20

300

us

1,3

Tfall

tF

Fall time of single-ended control inputs

5

ns

2

Trise

tR

Rise time of single-ended control inputs

5

ns

2

SMBus Input Low Voltage

VILSMB

VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V

0.6

V

SMBus Input High Voltage

VIHSMB

VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V

2.1

3.6

V

4

SMBus Output Low Voltage

VOLSMB

@ IPULLUP

0.4

V

SMBus Sink Current

IPULLUP

@ VOL

4mA

Nominal Bus Voltage

VDDSMB

1.7

3.6

V

SCLK/SDATA Rise Time

tRSMB

(Max VIL - 0.15) to (Min VIH + 0.15)

1000

ns

1

SCLK/SDATA Fall Time

tFSMB

(Min VIH + 0.15) to (Max VIL - 0.15)

300

ns

1

SMBus Operating

Frequency

fMAXSMB

Maximum SMBus operating frequency

400

kHz

1

1 Guaranteed by design and characterization, not 100% tested in production.

2 Control input must be monotonic from 20% to 80% of input swing.

Input Current

Ambient Operating

Temperature

TAMB

Capacitance

3 Time from deassertion until outputs are >200 mV

4 For V

DDSMB < 3.3V, VIHSMB >= 0.65xVDDSMB

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