9FGV0241AKLF datasheet(1/16 Pages) IDT

Part #	9FGV0241AKLF

Description	2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

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Manufacturer	IDT [Integrated Device Technology]

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DATASHEET

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

9FGV0241

IDT®

2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR

1

9FGV0241

JUNE 22, 2017

Description

The 9FGV0241 is a 2-output very low power frequency

generator for PCIe Gen 1, 2, 3 and 4 applications with

integrated output terminations providing Zo=100

. The

device has 2 output enables for clock management and

supports 2 different spread spectrum levels in addition to

spread off.

Recommended Application

PCIe Gen1-4 clock generation for Riser Cards, Storage,

Networking, JBOD, Communications, Access Points

Output Features

• 2 – 0.7V low-power HCSL-compatible (LP-HCSL) DIF

pairs w/Zo=100



• 1 – 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)

support

Key Specifications

• DIF cycle-to-cycle jitter <50ps

• DIF output-to-output skew <50ps

• DIF phase jitter is PCIe Gen1-2-3-4 compliant

• REF phase jitter is <1.5ps RMS

Features/Benefits

• Integrated terminations provide 100 differential Zo;

reduced component count and board space

• 1.8V operation; reduced power consumption

• OE# pins; support DIF power management

• LP-HCSL differential clock outputs; reduced power and

board space

• Programmable Slew rate for each output; allows tuning

for various line lengths

• Programmable output amplitude; allows tuning for

various application environments

• DIF outputs blocked until PLL is locked; clean system

start-up

• Selectable 0%, -0.25% or -0.5% spread on DIF outputs;

reduces EMI

• External 25MHz crystal; supports tight ppm with 0 ppm

synthesis error

• Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

• 3.3V tolerant SMBus interface works with legacy

controllers

• Space saving 24-pin 4x4 mm VFQFPN; minimal board

space

Block Diagram

XIN/CLKIN_25

X2

vSS_EN_tri

^CKPWRGD_PD#

SDATA_3.3

REF

vOE(1:0)#

SCLK_3.3

vSADR

DIF0

DIF1

2

IDT 603-25-150JA4C or

603-25-150JA4I 25MHz

SSC Capable

PLL

Control

Logic

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