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5L35021-000NDGI8 Datasheet(PDF) 3 Page - Integrated Device Technology |
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5L35021-000NDGI8 Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 37 page 3 ©2017 Integrated Device Technology, Inc. July 13, 2017 5L35021 Datasheet Detailed Block Diagram 14 DIFF1B Output Differential clock output 1_Complement; can be OTP pre-programmed to LVCMOS/LPHCSL output type. 15 DIFF1 Output Differential clock output 1_True; can be OTP pre-programmed to LVCMOS/LPHCSL output type. 16 VSSDIFF1 Power Connect to ground. 17 VDDDIFF2 Power Output power supply. Connect to 1.8V. Sets output voltage levels for DIFF2. 18 DIFF2B Output Differential clock output 2_Complement; can be OTP pre-programmed to LVCMOS/LPHCSL output type. 19 DIFF2 Output Differential clock output 2_True; can be OTP pre-programmed to LVCMOS/LPHCSL output type. 20 VSSDIFF2 Power Connect to ground. EPAD Power Connect to ground pad. Table 1. Pin Descriptions (Cont.) Number Name Type Description Overshot Reduction (ORT) OSC PLL2 DIV 3 DIFF2 DIFF2B DIFF1 DIFF1B SE1 PLL1 DIV 1 DIV 5 PLL3 DIV 4 DIV 2 OE1 CLKIN/X2 CLKINB/X1 SDA_DFC0 SCL_DFC1 OTP memory (1 configuration) MUX MUX MUX MUX MUX MUX MUX MUX MUX MUX 32K DIV5 DIV4/REF DIV3 DIV1/REF DIV1/REF DIV3 Proactive Power Saving Logic (PPS) I2C Engine VDDSE1 VDDDIFF1 VDDDIFF2 Timer Dynamic Frequency Control Logic (DFC) POR Power Monitor VDD18 VBAT 32.768K DCO Calibration VSS VDDA MUX MUX MUX MUX |
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