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AKD4641 Datasheet(PDF) 11 Page - Asahi Kasei Microsystems |
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AKD4641 Datasheet(HTML) 11 Page - Asahi Kasei Microsystems |
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11 / 51 page  ASAHI KASEI [AK4641] MS0301-E-00 2004/05 - 11 - Parameter Symbol min typ max Units 16bit Mono CODEC Interface Timing: SYNC Timing Frequency (PLL Lock Range) Bfs 8 - 16 kHz Serial Interface Timing at Short/long Frame Sync BBICK Frequency fBBCK 128 2048 kHz BBICK Period tBBCK 488 ns BBICK duty cycle tBDUT 50 % BBICK Pulse Width Low tBBCKL 200 ns Pulse Width High tBBCKH 200 ns BSYNC Edge to BBICK “ ↓ ” tBSYB 50 ns BBICK “ ↓ ” to BSYNC Edge tBBSY 50 ns BSYNC to BSDTO (MSB) (Except Short Frame) tBSYD 80 ns BBICK “ ↑ ” to BSDTO tBBSD 80 ns BSDTI Hold Time tBSDH 50 ns BSDTI Setup Time tBSDS 50 ns BSYNC Pulse Width Low tBBSL 3300 ns Pulse Width High tBBSH 440 ns Serial Interface Timing at MSB justified and I 2S BBICK Frequency fBBCK 256 2048 kHz BBICK Period tBBCK 488 ns BBICK duty cycle tBDUT 50 % BBICK Pulse Width Low tBBCKL 200 ns Pulse Width High tBBCKH 200 ns BSYNC Edge to BBICK “ ↑ ” tBSYB2 50 ns BBICK “ ↑ ” to BSYNC Edge tBBSY2 50 ns BSYNC to BSDTO (MSB) (Except I 2S mode) tBSYD2 80 ns BBICK “ ↓ ” to BSDTO tBBSD2 80 ns BSDTI Hold Time tBSDH2 50 ns BSDTI Setup Time tBSDH2 50 ns BSYNC Duty Cycle BDuty2 45 50 55 % Control Interface Timing (I 2C Bus mode): SCL Clock Frequency fSCL - 400 kHz Bus Free Time Between Transmissions tBUF 1.3 - µs Start Condition Hold Time (prior to first clock pulse) tHD:STA 0.6 - µs Clock Low Time tLOW 1.3 - µs Clock High Time tHIGH 0.6 - µs Setup Time for Repeated Start Condition tSU:STA 0.6 - µs SDA Hold Time from SCL Falling (Note 21) tHD:DAT 0 - µs SDA Setup Time from SCL Rising tSU:DAT 0.1 - µs Rise Time of Both SDA and SCL Lines tR - 0.3 µs Fall Time of Both SDA and SCL Lines tF - 0.3 µs Setup Time for Stop Condition TSU:STO 0.6 - µs Pulse Width of Spike Noise Suppressed by Input Filter tSP 0 50 ns Reset Timing PDN Pulse Width (Note 22) tPD 150 ns PMADC “ ↑” to SDTO valid (Note 23) tPDV 2081 1/fs PMAD2 “ ↑” to BSDTO valid (Note 24) tBPDV 1057 1/Bfs Note 21. Data must be held long enough to bridge the 300ns-transition time of SCL. Note 22. The AK4641 can be reset by the PDN pin = “L”. Note 23. This is the count of LRCK “ ↑” from the PMADC bit = “1”. Note 24. This is the count of BSYNC “ ↑” from the PMAD2 bit = “1”. Purchase of Asahi Kasei Microsystems Co., Ltd I 2C components conveys a license under the Philips I 2C patent to use the components in the I2C system, provided the system conform to the I2C specifications defined by Philips. |
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