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CS497014 Datasheet(PDF) 15 Page - Cirrus Logic

Part No. CS497014
Description  High Definition Audio Decoder DSP Family with Dual 32-bit Engine Technology
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Maker  CIRRUS [Cirrus Logic]
Homepage  http://www.cirrus.com
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CS497014 Datasheet(HTML) 15 Page - Cirrus Logic

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CS4970x4 Data Sheet
32-bit High Definition Audio Decoder DSP Family
DS752F1
15
5.11 Switching Characteristics — Serial Control Port - I2C Slave Mode
Figure 5. Serial Control Port - I2C Slave Mode Timing
Parameter
Symbol
Min
Typical
Max
Units
SCP_CLK frequency1
1. The specification fiicck indicates the maximum speed of the hardware. The system designer should be aware that the actual
maximum speed of the communication port may be limited by the firmware application. Flow control using the SCP_
BSY pin
should be implemented to prevent overflow of the input data buffer.
fiicck
——
400
kHz
SCP_CLK low time
tiicckl
1.25
µs
SCP_CLK high time
tiicckh
1.25
µs
SCP_SCK rising to SCP_SDA rising or falling for START or
STOP condition
tiicckcmd
1.25
µs
START condition to SCP_CLK falling
tiicstscl
1.25
µs
SCP_CLK falling to STOP condition
tiicstp
2.5
µs
Bus free time between STOP and START conditions
tiicbft
3—
µs
Setup time SCP_SDA input valid to SCP_CLK rising
tiicsu
100
ns
Hold time SCP_SDA input after SCP_CLK falling2
2. This parameter is measured from the ViL level at the falling edge of the clock.
tiich
0—
ns
SCP_CLK low to SCP_SDA out valid
tiicdov
——
18
ns
SCP_CLK falling to SCP_IRQ rising
tiicirqh
——
3*DCLKP + 40
ns
NAK condition to SCP_IRQ low
tiicirql
—3*DCLKP + 20
ns
SCP_CLK rising to SCB_BSY low
tiicbsyl
—3*DCLKP + 20
ns
SCP_BSY#
SCP_CLK
SCP_SDA
SCP_IRQ#
0
1
6
780
1
7
tiicckl
tiicckh
tiicsu
tiich
A6
A0
R/W
ACK
LSB
tiicirqh
tiicirql
8
ACK
MSB
tiicstp
6
tiiccbsyl
tiicdov
tiicbft
tiicstscl
tiicckcmd
fiicck
tiicckcmd
tiicf
tiicr


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