ADS808

2

SBAS179C

www.ti.com

ELECTRICAL CHARACTERISTICS

SPECIFIED

PACKAGE

TEMPERATURE

PACKAGE

ORDERING

TRANSPORT

PRODUCT

PACKAGE-LEAD

RANGE

MARKING

NUMBER

MEDIA, QUANTITY

ADS808Y

TQFP-48

PHP

–40

°C to +85°C

ADS808Y

ADS808Y/250

Tape and Reel, 250

""

"

"

"

ADS808Y/2K

Tape and Reel, 2000

NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com.

PACKAGE/ORDERING INFORMATION

Case Temperature ......................................................................... +100

°C

Junction Temperature .................................................................... +150

°C

Storage Temperature ..................................................................... +150

°C

NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings”

may cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas

Instruments recommends that all integrated circuits be handled

with appropriate precautions. Failure to observe proper han-

dling and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

ADS808Y

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

RESOLUTION

12 Tested

Bits

SPECIFIED TEMPERATURE RANGE

Ambient Air

–40 to +85

°C

ANALOG INPUT

Standard Differential Input Range

(1Vp-p • 2, +10dBm)

1

2

V

Single-Ended Input Voltage

1Vp-p

2

3

V

Common-Mode Voltage

2.5

V

Optional Input Ranges

Selectable

1Vp-p or 1.5Vp-p

V

Analog Input Bias Current

1

µA

Track-Mode Input Bandwidth

–3dBFS

1

GHz

Input Impedance

Static, No Clock

1.25 || 9

M

Ω || pF

CONVERSION CHARACTERISTICS

Sample Rate

1M

70M

Samples/s

Data Latency

5

Clk Cyc

DYNAMIC CHARACTERISTICS

Differential Linearity Error (largest code error)

f = 1MHz

±0.7

+1.7/–1.0

LSB

No Missing Codes

Tested

Integral Nonlinearity Error, f = 1MHz

±4.0

±7.0

LSBs

f = 1MHz

72

f = 10MHz

65

68

dBFS

2-Tone Intermodulation Distortion

–77

dBFS

Signal-to-Noise Ratio (SNR)

f = 1MHz

64.5

dBFS

f = 10MHz

64

dBFS

Signal-to-(Noise + Distortion) (SINAD)

f = 2.2MHz

64

dBFS

f = 10MHz

63

dBFS

Output Noise

Input AC-Grounded

0.3

LSBs rms

Aperture Delay Time

3ns

Aperture Jitter

0.25

ps rms

Over-Voltage Recovery Time

2ns

Full-Scale Step Acquisition Time

5ns

DIGITAL INPUTS

Logic Family

+3V/+5V Logic Compatible CMOS

Convert Command

Start Conversion

Rising Edge of Convert Clock

100

µA

±10

µA

High-Level Input Voltage

+2.0

V

Low-Level Input Voltage

+1.0

V

Input Capacitance

5pF