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N76E003 Datasheet(PDF) 9 Page - List of Unclassifed Manufacturers |
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N76E003 Datasheet(HTML) 9 Page - List of Unclassifed Manufacturers |
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9 / 267 page  N76E003 Datasheet Jun 26, 2017 Page 9 of 267 Rev. 1.02 3. BLOCK DIAGRAM Figure 3-1 shows the N76E003 functional block diagram and gives the outline of the device. User can find all the peripheral functions of the device in the diagram. 1T High Performance 8051 Core Max. 18K Bytes APROM Flash 256 Bytes Internal RAM 768 Bytes XRAM (Auxiliary RAM) P0 P1 P2 P3 PWM Watchdog Timer Clock Divider Serial Ports (UARTs) Timer 0/1 Power-on Reset and Brown-out Detection I 2C P0[7:0] P1[7:0] P20 P30 INT1 (P1.7) INT0 (P3.0) RXD (P0.7 or P0.6) TXD (P0.6 or P0.7) SDA (P1.4 or P1.6) SCL (P1.3 or P0.2) PWM0~PWM5 (P1.5, P1.4, P1.2, P1.1, P1.0, P0.0, P0.1, P0[3:5]) External Interrupt T1 (P0.0) T0 (P0.5) VDD GND 16 MHz/10 kHz Internal RC Oscillator RST 8 8 1 System Clock Power Managment 10 Pin Interrupt Any Port 8 Timer 2 with Input Capture IC0~IC7 (P1.5, P1[2:0], P0.0, P0.1, P0[5:3]) [1] P2.0 is shared with RST. [2] P3.0 is shared with XIN. RXD_1 (P0.2) TXD_1 (P1.6) FB (P1.4) SPI MISO (P0.1) MOSI (P0.0) SPCLK (P1.0) SS (P1.5) 12-bit ADC AIN0~7 (P1.7, P3.0, P0[7:3], P0.1) 8 STADC (P1.3 or P0.4) Self Wake-up Timer Max. 4K Bytes LDROM Flash Timer 3 [1] [1] XIN [2] [2] 9 1 Figure 3-1. Functional Block Diagram |
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