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ADC1034 Datasheet(PDF) 4 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. ADC1034
Description  ADC1031/ADC1034/ADC1038 10-Bit Serial I/O A/D Converters with Analog Multiplexer and Track/Hold Function
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com

ADC1034 Datasheet(HTML) 4 Page - National Semiconductor (TI)

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Electrical Characteristics (Continued)
The following specifications apply for VCC ea50V VREF ea46V fS e 700 kHz and fC e 3 MHz unless otherwise
specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C
(Note 8)
(Note 9)
DO Hold Time from SCLK Falling Edge
RL e 30 kX CL e 100 pF
ns (min)
Delay from SCLK Falling
RL e 30 kX CL e 100 pF
ns (max)
Edge to DO Data Valid
DO Rise Time
RL e 30 kX
ns (max)
CL e 100 pF
Low to High
ns (max)
DO Fall Time
RL e 30 kX
ns (max)
CL e 100 pF
High to Low
ns (max)
Input Capacitance
Analog Inputs (CH0 – CH7)
All Other Inputs
Note 1
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur
Note 2
Operating Ratings indicate conditions for which the device is functional but do not guarantee specific performance limits For guaranteed specifications
and test conditions see the Electrical Characteristics The guaranteed specifications apply only for the test conditions listed Some performance characteristics
may degrade when the device is not operated under the listed test conditions
Note 3
All voltages are measured with respect to AGND and DGND unless otherwise specified
Note 4
When the input voltage (VIN) at any pin exceeds the power supplies (VIN k DGND or VIN l VCC) the current at that pin should be limited to 5 mA The
20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four pins
Note 5
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJmax iJA and the ambient temperature TA The maximum
allowable power dissipation at any temperature is PD e (TJmax b TA) iJA or the number given in the Absolute Maximum Ratings whichever is lower For this
device TJmax e 125 C The typical thermal resistance (iJA) of these parts when board mounted follow ADC1031 with CIN suffixes 71 CW ADC1034 with CMJ
suffixes 52 CW ADC1034 with CIN suffixes 54 CW ADC1034 with CIWM suffixes 70 CW ADC1038 with CMJ suffixes 53 CW ADC1038 with CIN suffixes
46 CW ADC1038 with CIWM suffixes 64 CW
Note 6
Human body model 100 pF capacitor discharged through a 15 kX resistor
Note 7
See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or
Linear Databook section ‘‘Surface Mount’’ for other methods of
soldering surface mount devices
Note 8
Typicals are at TJ e 25 C and represent most likely parametric norm
Note 9
Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level)
Note 10
Total unadjusted error includes offset full-scale linearity multiplexer and hold step errors
Note 11
Two on-chip diodes are tied to each analog input They will forward-conduct for analog input voltages one diode drop below ground or one diode drop
greater than VCC supply Be careful during testing at low VCC levels (45V) as high level analog inputs (5V) can cause an input diode to conduct especially at
elevated temperatures which will cause errors for analog inputs near full-scale The spec allows 50 mV forward bias of either diode this means that as long as the
analog VIN does not exceed the supply voltage by more than 50 mV the output code will be correct Exceeding this range on an unselected channel will corrupt the
reading of a selected channel To achieve an absolute 0 VDC to5VDC input voltage range will therefore require a minimum supply voltage of 4950 VDC over
temperature variations initial tolerance and loading
Note 12
Channel leakage current is measured after the channel selection
Note 13
In order to synchronize the serial data exchange properly SARS needs to go low after completion of the serial IO data exchange If this does not occur
the output shift register will be reset and the correct output data lost The minimum limit for SCLK will depend on CCLK frequency and whether right-justified or left-
justified and can be determined by the following equations
fS l (8541) (fC) with right-justification (RL e ‘‘1’’) and fS l (2541) (fC) with left-justification (RL e ‘‘0’’)

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