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ADC1034 Datasheet(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part No. ADC1034
Description  ADC1031/ADC1034/ADC1038 10-Bit Serial I/O A/D Converters with Analog Multiplexer and Track/Hold Function
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Maker  NSC [National Semiconductor (TI)]
Homepage  http://www.national.com
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ADC1034 Datasheet(HTML) 3 Page - National Semiconductor (TI)

 
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Electrical Characteristics (Continued)
The following specifications apply for VCC ea50V VREF ea46V fS e 700 kHz and fC e 3 MHz unless otherwise
specified Boldface limits apply for TA e TJ e TMIN to TMAX all other limits TA e TJ e 25 C
Symbol
Parameter
Conditions
Typical
Limit
Units
(Note 8)
(Note 9)
(Limits)
DIGITAL AND DC CHARACTERISTICS
VIN(1)
Logical ‘‘1’’ Input Voltage
VCC e 525 VDC
20
V (min)
VIN(0)
Logical ‘‘0’’ Input Voltage
VCC e 475 VDC
08
V (max)
IIN(1)
Logical ‘‘1’’ Input Current
VIN e 50 VDC
0005
25
m
A (max)
IIN(0)
Logical ‘‘0’’ Input Current
VIN e 0VDC
b
0005
b
25
m
A (max)
VOUT(1) Logical ‘‘1’’ Output Voltage
VCC e 475 VDC
IOUT eb360 mA
24
V (min)
IOUT eb10 mA
45
V (min)
VOUT(0) Logical ‘‘0’’ Output Voltage
VCC e 475 VDC
04
V (max)
IOUT e 16 mA
IOUT
TRI-STATE Output Current
VOUT e 0V
b
001
b
3
m
A (max)
VOUT e 5V
001
3
m
A (max)
ISOURCE Output Source Current
VOUT e 0V
b
14
b
65
mA (min)
ISINK
Output Sink Current
VOUT e VCC
16
80
mA (min)
ICC
Supply Current
CS e HIGH VREF Open
15
3
mA (max)
AC CHARACTERISTICS
fC
Conversion Clock (CCLK)
07
MHz (min)
Frequency
40
30
MHz (max)
fS
Serial Data Clock (SCLK)fC e 3 MHz RL e ‘‘0’’
183
kHz (min)
Frequency (Note 13)
fC e 3 MHz RL e ‘‘1’’
622
kHz (min)
fC e 3 MHz RL e ‘‘0’’ or RL e ‘‘1’’
2
10
MHz (max)
TC
Conversion Time
Not Including MUX Addressing and
41 (1fC)
(max)
Analog Input Sampling Times
a
200 ns
tCA
Analog Sampling Time
After Address is LatchedCS e Low
45 (1fS)
(max)
a
200 ns
tACC
Access Time Delay from CS or OE
OE e ‘‘0’’
100
200
ns (max)
Falling Edge to DO Data Valid
tSET-UP
Set-up Time of CS Falling
75
150
ns (min)
Edge to SCLK Rising Edge
t1H t0H
Delay from OE or CS Rising
RL e 3kX CL e 100 pF
100
120
ns (max)
Edge to DO TRI-STATE
tHDI
DI Hold Time from SCLK Rising Edge
0
50
ns (min)
tSDI
DI Set-up Time to SCLK Rising Edge
50
100
ns (min)
3


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