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WM8912 Datasheet(PDF) 15 Page - Cirrus Logic |
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WM8912 Datasheet(HTML) 15 Page - Cirrus Logic |
15 / 129 page Production Data WM8912 w PD, Rev 4.1, February 2013 15 AUDIO INTERFACE TIMING MASTER MODE Figure 2 Audio Interface Timing – Master Mode Test Conditions DCVDD = 1.0V, AVDD = DBVDD = CPVDD = 1.8V, DGND=AGND=CPGND =0V, TA = +25 oC, Master Mode, fs=48kHz, MCLK=256fs, 24-bit data, unless otherwise stated. PARAMETER SYMBOL MIN TYP MAX UNIT Audio Interface Timing - Master Mode LRCLK propagation delay from BCLK falling edge tDL 20 ns DACDAT setup time to BCLK rising edge tDST 20 ns DACDAT hold time from BCLK rising edge tDHT 10 ns |
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