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CAT28LV64W-20T Datasheet(PDF) 1 Page - Catalyst Semiconductor |
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CAT28LV64W-20T Datasheet(HTML) 1 Page - Catalyst Semiconductor |
1 / 12 page 1 © 2004 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice ■ CMOS and TTL compatible I/O ■ Automatic page write operation: – 1 to 32 bytes in 5ms – Page load timer ■ End of write detection: – Toggle bit – DATA DATA DATA DATA DATA polling ■ Hardware and software write protection ■ 100,000 program/erase cycles ■ 100 year data retention CAT28LV64 64K-Bit CMOS PARALLEL EEPROM DESCRIPTION The CAT28LV64 is a low voltage, low power, CMOS parallel EEPROM organized as 8K x 8-bits. It requires a simple interface for in-system programming. On-chip address and data latches, self-timed write cycle with auto- clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the self- timed write cycle. Additionally, the CAT28LV64 features hardware and software write protection. The CAT28LV64 is manufactured using Catalyst’s advanced CMOS floating gate technology. It is designed to endure 100,000 program/erase cycles and has a data retention of 100 years. The device is available in JEDEC approved 28-pin DIP, 28-pin TSOP, 28-pin SOIC or 32- pin PLCC packages. BLOCK DIAGRAM FEATURES ■ 3.0V to 3.6 V Supply ■ Read access times: – 150/200/250ns ■ Low power CMOS dissipation: – Active: 8 mA max. – Standby: 100 µA max. ■ Simple write operation: – On-chip address and data latches – Self-timed write cycle with auto-clear ■ Fast write cycle time: – 5ms max. ■ Commercial, industrial and automotive temperature ranges Doc. No. 1010, Rev. D ADDR. BUFFER & LATCHES ADDR. BUFFER & LATCHES INADVERTENT WRITE PROTECTION CONTROL LOGIC TIMER ROW DECODER COLUMN DECODER HIGH VOLTAGE GENERATOR A5–A12 CE OE WE A0–A4 I/O0–I/O7 I/O BUFFERS 8,192 x 8 E2PROM ARRAY 32 BYTE PAGE REGISTER VCC DATA POLLING AND TOGGLE BIT ALO GEN FR TM LEAD FREE |
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