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XR16C2850IJ Datasheet(PDF) 8 Page - Exar Corporation |
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XR16C2850IJ Datasheet(HTML) 8 Page - Exar Corporation |
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8 / 44 page  XR16C2850 8 Rev. 1.00P GENERAL DESCRIPTION The XR16C2850 provides serial asynchronous re- ceive data synchronization, parallel-to-serial and se- rial-to-parallel data conversions for both the transmit- ter and receiver sections. These functions are neces- sary for converting the serial data stream into parallel data that is required with digital data systems. Syn- chronization for the serial data stream is accom- plished by adding start and stops bits to the transmit data to form a data character (character orientated protocol). Data integrity is insured by attaching a parity bit to the data character. The parity bit is checked by the receiver for any transmission bit errors. The elec- tronic circuitry to provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip. The XR16C2850 represents such an integration with greatly enhanced features. The 2850 is fabricated with an advanced CMOS process. The 2850 is an upward solution that provides 128 bytes of transmit and receive FIFO memory, instead of 16 bytes provided in the 16C2550. The 2850 is designed to work with high speed modems and shared network environments, that require fast data process- ing time. Increased performance is realized in the 2850 by the larger transmit and receive FIFO. This allows the external processor to handle more network- ing tasks within a given time. For example, the ST16C2550 with a 16 byte FIFO, unloads 16 bytes of receive data in 1.53 ms (this example uses a character length of 11 bits, including start/stop bits at 115.2Kbps). This means the external CPU will have to service the receive FIFO at 1.53 ms intervals. How- ever with the 128 byte FIFO in the 2850, the data buffer will not require unloading/loading for 12.2 ms. This increases the service interval giving the external CPU additional time for other applications and reduc- ing the overall UART interrupt servicing time. In addition, the programmable levels of FIFO trigger interrupt and automatic hardware/software flow con- trol is uniquely provided for maximum data throughput performance especially when operating in a multi- channel environment. The combination of the above greatly reduces the bandwidth requirement of the external controlling CPU, increases performance, and reduces power consumption. The 2850 provides RS-485 half dulpex control signal to select the external transceiver direction. Auto RS- 485 control pin (-RTS) is not activated after reset. To activate the direction control function, user has to set EFR Bit-4, and FCTR Bit-3 to 1. The -RTS pin is normally high for receive mode and it will go low when transmitter starts transmitting data. FUNCTIONAL DESCRIPTIONS UART A-B Functions The UART provides the user with the capability to Bi- directionally transfer information between an external CPU and an external serial communication device. A logic 0 on chip select pins -CSA and/or -CSB allows the user to configure, send data, and/or receive data via UART channels A-B. Individual channel select functions are shown in Table 2 below. Table 2, SERIAL PORT SELECTION GUIDE CHIP SELECT Function -CS A-B = 1s None -CS A = 0 UART CHANNEL A -CS B = 0 UART CHANNEL B Internal Registers The 2850 provides 15 internal registers for monitoring and control. These resisters are shown in Table 3. Twelve registers are similar to those already available in the standard 16C2550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (IER/ISR), a FIFO control regis- ter (FCR), line status and control registers, (LCR/ LSR), modem status and control registers (MCR/ MSR), programmable data rate (clock) control regis- ters (DLL/DLM), and a user accessible scratchpad register (SPR). Beyond the general 16C2550 features and capabilities, the 2850 offers an enhanced feature register set (EFR, Xon/Xoff 1-2) that provides on board hardware/software flow control. Register func- tions are more fully described in the following para- graphs. |
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