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NUC120RD1DN Datasheet(PDF) 76 Page - List of Unclassifed Manufacturers |
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NUC120RD1DN Datasheet(HTML) 76 Page - List of Unclassifed Manufacturers |
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76 / 107 page  NUC100/120xxxDN Mar. 02, 2017 Page 76 of 107 Rev 1.02 UART Interface Controller (UART) 6.14 The NuMicro ® NUC100 series provides up to three channels of Universal Asynchronous Receiver/Transmitters (UART). UART0 supports High Speed UART and UART1~2 perform Normal Speed UART. Besides, only UART0 and UART1 support the flow control function. 6.14.1 Overview The Universal Asynchronous Receiver/Transmitter (UART) performs a serial-to-parallel conversion on data received from the peripheral, and a parallel-to-serial conversion on data transmitted from the CPU. The UART controller also supports IrDA SIR, LIN master/slave mode and RS-485 mode functions. Each UART channel supports seven types of interrupts including: Transmitter FIFO empty interrupt (INT_THRE) Receiver threshold level reached interrupt (INT_RDA), Line status interrupt (parity error or frame error or break interrupt) (INT_RLS), Receiver buffer time-out interrupt (INT_TOUT), MODEM/Wake-up status interrupt (INT_MODEM), Buffer error interrupt (INT_BUF_ERR) LIN interrupt (INT_LIN) Interrupts of UART0 and UART2 share the interrupt number 12 (vector number is 28); Interrupt number 13 (vector number is 29) only supports UART1 interrupt. Refer to the Nested Vectored Interrupt Controller chapter for System Interrupt Map. The UART0 is built-in with a 64-byte transmitter FIFO (TX_FIFO) and a 64-byte receiver FIFO (RX_FIFO) that reduces the number of interrupts presented to the CPU. The UART1~2 are equipped with 16-byte transmitter FIFO (TX_FIFO) and 16-byte receiver FIFO (RX_FIFO). The CPU can read the status of the UART at any time during the operation. The reported status information includes the type and condition of the transfer operations being performed by the UART, as well as 4 error conditions (parity error, frame error, break interrupt and buffer error) probably occur while receiving data. The UART includes a programmable baud rate generator that is capable of dividing clock input by divisors to produce the serial clock that transmitter and receiver need. The baud rate equation is Baud Rate = UART_CLK / M * [BRD + 2], where M and BRD are defined in Baud Rate Divider Register (UA_BAUD). Table 6-6 lists the equations in the various conditions and Table 6-7 lists the UART baud rate setting table. Mode DIV_X_EN DIV_X_ONE Divider X BRD Baud Rate Equation 0 0 0 Don’t care A UART_CLK / [16 * (A+2)] 1 1 0 B A UART_CLK / [(B+1) * (A+2)] , B must >= 8 2 1 1 Don’t care A UART_CLK / (A+2), A must >=3 Table 6-6 UART Baud Rate Equation System Clock = Internal 22.1184 MHz High Speed Oscillator Baud Rate Mode 0 Mode 1 Mode 2 Parameter Register Parameter Register Parameter Register 921600 x x A=0,B=11 0x2B00_0000 A=22 0x3000_0016 |
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