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R7FS7G27H3A01CFB Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # R7FS7G27H3A01CFB
Description  32-bit ARM Cortex-M4 microcontroller
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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R01DS0262EU0100 Rev.1.00
Page 6 of 113
Feb 23, 2016
S7G2
1. Overview
Ethernet MAC with IEEE 1588 PTP
(ETHERC)
Two-channel Ethernet MAC Controller (ETHERC) compliant with the Ethernet/IEEE802.3
Media Access Control (MAC) layer protocol. Each ETHERC channel provides one channel of
the MAC layer interface, connecting the MCU to the physical layer LSI (PHY-LSI) that allows
transmission and reception of frames compliant with the Ethernet and IEEE802.3 standards.
The ETHERC is connected to the Ethernet DMA Controller (EDMAC) so data can be
transferred without using the CPU.
To handle timing and synchronization between devices, an on-chip Precision Time Protocol
(PTP) module for the Ethernet PTP Controller (EPTPC) applies the PTP defined in the IEEE
1588-2008 version 2.0 standard.
The EPTPC is composed of:
 Synchronization Frame Processing units (SYNFP0 and SYNFP1)
 A Packet Relation Controller unit (PRC-TC)
 A Statistical Time Correction Algorithm unit (STCA).
Use the EPTPC in combination with the on-chip Ethernet MAC Controller (ETHERC) and the
DMA Controller for the PTP Ethernet Controller (PTPEDMAC). See section 29, Ethernet MAC
Controller (ETHERC) in User's Manual.
SD/MMC Host Interface (SDHI)
The SDHI and MultiMediaCard (MMC) interface provide the functionality required to connect a
variety of external memory cards to the MCU. The SDHI supports both 1- and 4-bit buses for
connecting memory cards that support SD, SDHC, and SDXC formats. When developing host
devices that are compliant with the SD Specifications, you must comply with the SD
Host/Ancillary Product License Agreement (SD HALA).
The MMC interface supports 1-, 4-, and 8-bit MMC buses that provide eMMC 4.51 (JEDEC
Standard JESD 84-B451) device access. This interface also provides backward compatibility
and supports high-speed SDR transfer modes. See section 43, SD/MMC Host Interface
(SDHI) in User's Manual.
Table 1.10
Analog
Feature
Functional description
12-Bit A/D Converter (ADC12)
Up to two successive approximation 12-Bit A/D Converters are provided. In unit 0, up to 13
analog input channels are selectable. In unit 1, up to 12 analog input channels, the
temperature sensor output, and an internal reference voltage are selectable for conversion.
The A/D conversion accuracy is selectable from 12-, 10-, and 8-bit conversion, making it
possible to optimize the tradeoff between speed and resolution in generating a digital value.
See section 46, 12-Bit A/D Converter (ADC12) in User's Manual.
12-Bit D/A Converter (DAC12)
The DAC12 D/A converts data and includes an output amplifier. See section 47, 12-Bit D/A
Converter (DAC12) in User's Manual.
Temperature sensor (TSN)
The on-chip temperature sensor can determine and monitor the die temperature for reliable
operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC12 for conversion and can also be used by the end
application. See section 48, Temperature Sensor (TSN) in User's Manual.
High-Speed Analog Comparator
(ACMPHS)
Analog comparators can be used to compare a test voltage with a reference voltage and to
provide a digital output based on the conversion result.
Both the test and reference voltages can be provided to the comparator from internal sources
such as the DAC12 output and internal reference voltage, and an external source with or
without an internal PGA.
Such flexibility is useful in applications that require go/no-go comparisons to be performed
between analog signals without necessarily requiring A/D conversion. See section 49, High-
Speed Analog Comparator (ACMPHS) in User's Manual.
Table 1.11
Human machine interfaces (1/2)
Feature
Functional description
Key interrupt function (KINT)
A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 21, Key Interrupt Function
(KINT) in User's Manual.
Table 1.9
Communication interfaces (2/2)
Feature
Functional description


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