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R5F5110JADNE Datasheet(PDF) 67 Page - Renesas Technology Corp |
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R5F5110JADNE Datasheet(HTML) 67 Page - Renesas Technology Corp |
67 / 108 page R01DS0202EJ0120 Rev.1.20 Page 67 of 108 Jul 29, 2016 RX110 Group 5. Electrical Characteristics 5.3.2 Reset Timing Note 1. When OFS1.(STUPLVD1REN, FASTSTUP) = 11b. Note 2. When OFS1.(STUPLVD1REN, FASTSTUP) ≠ 11b. Note 3. When IWDTCR.CKS[3:0] = 0000b. Figure 5.25 Reset Input Timing at Power-On Figure 5.26 Reset Input Timing (1) Figure 5.27 Reset Input Timing (2) Table 5.23 Reset Timing Conditions: 1.8 V ≤ VCC ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = 0 V, T a = –40 to +105°C Item Symbol Min. Typ. Max. Unit Test Conditions RES# pulse width At power-on tRESWP 3 — — ms Figure 5.25 Other than above tRESW 30 — — μs Figure 5.26 Wait time after RES# cancellation (at power-on) At normal startup*1 tRESWT — 8.5 — ms Figure 5.25 During fast startup time*2 tRESWT —560 — μs Wait time after RES# cancellation (during powered-on state) tRESWT —114 — μs Figure 5.26 Independent watchdog timer reset period tRESWIW — 1 — IWDT clock cycle Figure 5.27 Software reset period tRESWSW — 1 — ICLK cycle Wait time after independent watchdog timer reset cancellation*3 tRESW2 —300 — μs Wait time after software reset cancellation tRESW2 —168 — μs VCC RES# tRESWP Internal reset tRESWT RES# Internal reset tRESWT tRESW Independent watchdog timer reset Software reset Internal reset tRESWT2 tRESWIW, tRESWSW |
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