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R5F565N7FDFB Datasheet(PDF) 2 Page - Renesas Technology Corp |
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R5F565N7FDFB Datasheet(HTML) 2 Page - Renesas Technology Corp |
2 / 190 page RX65N Group, RX651 Group 1. Overview R01DS0276EJ0100 Rev.1.00 Page 2 of 190 Aug 24, 2016 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications in outline, and Table 1.2 gives a comparison of the functions of products in different packages. Table 1.1 shows the outline of maximum specifications, and the number of peripheral module channels differs depending on the pin number on the package. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/8) Classification Module/Function Description CPU CPU Maximum operating frequency: 120 MHz 32-bit RX CPU (RXv2) Minimum instruction execution time: One instruction per state (cycle of the system clock) Address space: 4-Gbyte linear Register set of the CPU General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32 × 32 → 64 bits On-chip divider: 32 / 32 → 32 bits Barrel shifter: 32 bits FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory Code flash memory Capacity: 512 Kbytes/768 Kbytes/1 Mbyte 50 MHz No-wait cycle access 100 MHz 1-wait cycle access 100 MHz 2-wait cycle access Instructions hitting the ROM cache or operand = 120 MHz: No-wait access On-board programming: Four types Off-board programming (parallel programmer mode) The trusted memory (TM) function protects against the reading of programs from blocks 8 and 9. RAM Capacity: 256 Kbytes 120 MHz, no-wait access Standby RAM Capacity: 8 Kbytes Operation synchronized with PCLKB: Up to 60 MHz, two-cycle access Operating modes Operating modes by the mode-setting pins at the time of release from the reset state Single-chip mode Boot mode (for the SCI interface) Boot mode (for the USB interface) Boot mode (for the FINE interface) Selection of operating mode by register setting Single-chip mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Endian selectable |
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