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R5F523T5ADFD Datasheet(PDF) 2 Page - Renesas Technology Corp |
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R5F523T5ADFD Datasheet(HTML) 2 Page - Renesas Technology Corp |
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2 / 98 page  R01DS0248EJ0110 Rev.1.10 Page 2 of 98 Jan 13, 2016 RX23T Group 1. Overview 1. Overview 1.1 Outline of Specifications Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different packages. Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different Packages. Table 1.1 Outline of Specifications (1/3) Classification Module/Function Description CPU CPU Maximum operating frequency: 40 MHz 32-bit RX CPU (RX v2) Minimum instruction execution time: One instruction per clock cycle Address space: 4-Gbyte linear Register set General purpose: Sixteen 32-bit registers Control: Ten 32-bit registers Accumulator: Two 72-bit registers Basic instructions: 75 Variable-length instruction format Floating-point instructions: 11 DSP instructions: 23 Addressing modes: 11 Data arrangement Instructions: Little endian Data: Selectable as little endian or big endian On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit On-chip divider: 32-bit ÷ 32-bit → 32 bits Barrel shifter: 32 bits Memory protection unit (MPU) FPU Single precision (32-bit) floating point Data types and floating-point exceptions in conformance with the IEEE754 standard Memory ROM Capacity: 64 K/128 Kbytes 32 MHz, no-wait memory access 32 to 40 MHz: wait states Programming/erasing method: Serial programming (asynchronous serial communication), self-programming RAM Capacity: 12 Kbytes 40 MHz, no-wait memory access MCU operating mode Single-chip mode Clock Clock generation circuit Main clock oscillator, low-speed and high-speed on-chip oscillator, PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator Oscillation stop detection: Available Clock frequency accuracy measurement circuit (CAC): Available Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock (FCLK) The CPU and system sections such as other bus masters run in synchronization with the system clock (ICLK): 40 MHz (at max.) MTU3c runs in synchronization with the PCLKA: 40 MHz (at max.) Peripheral modules other than MTU3c run in synchronization with the PCLKB: 40 MHz (at max.) ADCLK operated in S12ADE runs in synchronization with the PCLKD: 40 MHz (at max.) The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.) Resets RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and software reset Voltage detection Voltage detection circuit (LVDAb) When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt is generated. Voltage detection circuit 0 is capable of selecting the detection voltage from 2 levels Voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels Low power consumption Low power consumption functions Module stop function Three low power consumption modes Sleep mode, deep sleep mode, and software standby mode Function for lower operating power consumption Operating power control modes High-speed operating mode and middle-speed operating mode |
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