TS83102G0BVGL datasheet(3/56 Pages) ATMEL

Part #	TS83102G0BVGL

Description	10-bit 2 Gsps ADC

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Manufacturer	ATMEL [ATMEL Corporation]

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TS83102G0B

2101D–BDC–06/04

Specification

Note:

Absolute maximum ratings are short term limiting values (referenced to GND = 0V), to be applied individually, while other

parameters are within specified operating conditions. Long exposure to maximum ratings may affect device reliability. All inte-

grated circuits have to be handled with appropriate care to avoid damage due to ESD. Damage caused by inappropriate

handling or storage could range from performance degradation to complete failure.

Absolute Maximum Ratings

Parameter

Symbol

Comments

Value

Unit

Positive supply voltage

VCC

GND to 6.0

V

Digital negative supply voltage

D

VEE

GND to -5.7

V

Digital positive supply voltage

VPLUSD

GND - 1.1 to 2.5

V

Negative supply voltage

VEE

GND to -5.5

V

Maximum difference between negative

supply voltages

DVEE to VEE

0.3

V

Analog input voltages

VIN or VINB

-1.5 to 1.5

V

Maximum difference between VIN and VINB

V

IN - VINB

-1.5 to 1.5

V

Clock input voltage

VCLK or VCLKB

-1 to 1

V

Maximum difference between VCLK and

VCLKB

VCLK - VCLKB

-1 to 1

Vpp

Static input voltage

VD

GA, SDA

-5 to 0.8

V

Digital input voltage

VD

SDAEN, DRRB, B/GB,

PGEB, DECB

-5 to 0.8

V

Digital output voltage

V

O

VPLUSD min operating -2.2 to

VPLUSD max operating + 0.8

V

Junction temperature

T

J

130

°C

Recommended Conditions of Use

Parameter

Symbol

Comments

Min

Typ

Max

Unit

Positive supply voltage

V

CC

4.75

5

5.25

V

Positive digital supply

voltage

V

PLUSD

Differential ECL output

compatibility

- 0.9

- 0.8

- 0.7

V

LVDS output compatibility

1.375

1.45

1.525

V

Grounded (1)

Maximum operating VPLUSD

1.7

V

Negative supply voltages

V

EE, DVEE

- 5.25

- 5.0

- 4.75

V

Differential analog input

voltage (full-scale)

V

IN, VINB

V

IN - VINB

50

Ω differential or single-ended

±113

450

±125

500

±137

550

mV

mVpp

Clock input power level

(ground common mode)

PCLK, PCLKB

50

Ω single-ended clock input or

100

Ω differential clock

(recommended)

- 4

0

4

dBm

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TS83102G0BVGL Datasheet(PDF) 3 Page - ATMEL Corporation

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