ESD8704

www.onsemi.com

7

Figure 14. USB 3.0/3.1 Standard Layout Diagram

Vbus

StdA_SSTX+

D−

StdA_SSTX−

D+

GND_DRAIN

GND

StdA_SSRX+

StdA_SSRX−

USB 3.0/3.1 Type A

Connector

ESD8704

ESD7L5.0

PCB Layout Guidelines

Steps must be taken for proper placement and signal trace

routing of the ESD protection device in order to ensure the

maximum ESD survivability and signal integrity for the

application. Such steps are listed below.

the I/O connector to reduce the ESD path to ground and

improve the protection performance.

should be placed between the AC coupling

capacitors and the I/O connector on the TX

differential lanes as shown in Figure 15. In this

configuration, no DC current can flow through the

ESD protection device preventing any potential

latch-up condition. For more information on latchup

considerations, see below description on Page 8.

impedance matching of all high speed signal traces.

reflections.

and negative lines of the differential data lanes to

avoid common mode noise generation and

impedance mismatch.

much distance between pairs as possible to reduce

crosstalk.

Figure 15. USB 3.0/3.1 Connection Diagram