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TC58512FT Datasheet(PDF) 4 Page - Toshiba Semiconductor

Part No. TC58512FT
Description  TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
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Maker  TOSHIBA [Toshiba Semiconductor]
Homepage  http://www.semicon.toshiba.co.jp/eng
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TC58512FT
2001-03-05
4/43
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
==== 0° to 70°C, VCC ==== 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
MAX
UNIT
NOTES
tCLS
CLE Setup Time
0
¾
ns
tCLH
CLE Hold Time
10
¾
ns
tCS
CE Setup Time
0
¾
ns
tCH
CE Hold Time
10
¾
ns
tWP
Write Pulse Width
25
¾
ns
tALS
ALE Setup Time
0
¾
ns
tALH
ALE Hold Time
10
¾
ns
tDS
Data Setup Time
20
¾
ns
tDH
Data Hold Time
10
¾
ns
tWC
Write Cycle Time
50
¾
ns
tWH
WE High Hold Time
15
¾
ns
tWW
WP High to WE Low
100
¾
ns
tRR
Ready to RE Falling Edge
20
¾
ns
tRP
Read Pulse Width
35
¾
ns
tRC
Read Cycle Time
50
¾
ns
tREA
RE Access Time (Serial Data Access)
¾
35
ns
tCEH
CE High Time for Last Address in Serial Read Cycle
100
¾
ns
(2)
tREAID
RE Access Time (ID Read)
¾
35
ns
tOH
Data Output Hold Time
10
¾
ns
tRHZ
RE High to Output High Impedance
¾
30
ns
tCHZ
CE High to Output High Impedance
¾
20
ns
tREH
RE High Hold Time
15
¾
ns
tIR
Output-High-impedance-to- RE Rising Edge
0
¾
ns
tRSTO
RE Access Time (Status Read)
¾
35
ns
tCSTO
CE Access Time (Status Read)
¾
45
ns
tRHW
RE High to WE Low
0
¾
ns
tWHC
WE High to CE Low
30
¾
ns
tWHR
WE High to RE Low
30
¾
ns
tAR1
ALE Low to RE Low (ID Read)
100
¾
ns
tCR
CE Low to RE Low (ID Read)
100
¾
ns
tR
Memory Cell Array to Starting Address
¾
25
ms
tWB
WE High to Busy
¾
200
ns
tAR2
ALE Low to RE Low (Read Cycle)
50
¾
ns
tRB
RE Last Clock Rising Edge to Busy (in Sequential Read)
¾
200
ns
tCRY
CE High to Ready (When interrupted by CE in Read Mode)
¾
1
+
tr (
BY
/
RY
)
ms
(1) (2)
tRST
Device Reset Time (Read/Program/Erase)
¾
6/10/500
ms
AC TEST CONDITIONS
PARAMETER
CONDITION
Input level
2.4 V, 0.4 V
Input pulse rise and fall time
3 ns
Input comparison level
1.5 V, 1.5 V
Output data comparison level
1.5 V, 1.5 V
Output load
CL (100 pF) + 1 TTL




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