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SN65LV1021DB Datasheet(PDF) 4 Page - Texas Instruments |
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SN65LV1021DB Datasheet(HTML) 4 Page - Texas Instruments |
4 / 19 page SN65LV1021/SN65LV1212 10-MHz TO 40-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER SLLS526F – FEBRUARY 2002 – REVISED NOVEMBER 2002 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 synchronization mode (continued) Start Bit Stop Bit DIN0 Held Low and DIN1 Held High DIN0 DIN1 Start Bit Stop Bit Start Bit Stop Bit DIN4 Held Low and DIN5 Held High DIN4 DIN5 Start Bit Stop Bit Start Bit Stop Bit DIN8 Held Low and DIN9 Held High DIN8 DIN9 Start Bit Stop Bit Figure 1. RMT Pattern Examples data transmission mode After initialization and synchronization, the serializer accepts parallel data from inputs DIN0–DIN9. The serializer uses the TCLK input to latch the incoming data. The TCLK_R/F pin selects which edge the serializer uses to strobe incoming data. If either of the SYNC inputs is high for 6 TCLK cycles, the data at DIN0–DIN9 is ignored regardless of the clock edge selected and 1026 cycles of SYNC pattern are sent. After determining which clock edge to use, a start and stop bit, appended internally, frames the data bits in the register. The start bit is always high and the stop bit is always low. The start and stop bits function as the embedded clock bits in the serial stream. The serializer transmits serialized data and appended clock bits (10+2 bits) from the serial data output (DO ±) at 12 times the TCLK frequency. For example, if TCLK is 10 MHz, the serial rate is 10 × 12 = 120 Mbps. Because only 10 bits are input data, the useful data rate is 10 times the TCLK frequency. For instance, if TCLK = 12 MHz, the useful data rate is 10 × 12 = 120 Mbps. The data source, which provides TCLK, must be in the range of 10 MHz to 40 MHz. |
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