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ACE25QA160G Datasheet(PDF) 8 Page - ACE Technology Co., LTD. |
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ACE25QA160G Datasheet(HTML) 8 Page - ACE Technology Co., LTD. |
8 / 29 page ACE25QA160G 16M BIT SPI NOR FLASH VER 1.1 8 Device Identification Three legacy Instructions are supported to access device identificati on that can indicate the manufacturer, device type, and capacity (density). The returned data bytes provide the information as shown in the below table. Table 5. ACE25QA160G ID Definition table Operation Code M7-M0 ID15-ID8 ID7-ID0 9FH 68 40 15 90H 68 14 ABH 14 Instructions Description All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 6, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being shifted out. For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must driven high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset. |
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