R5F524TAADFM datasheet(5/133 Pages) RENESAS

Part #	R5F524TAADFM

Description	32-bit RXv2 CPU core

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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R01DS0257EJ0200 Rev.2.00

Page 5 of 133

Apr 14, 2017

RX24T Group

1. Overview

12-bit A/D converter (S12ADF)

• 12 bits (5 channels × 2 units/12 channels × 1 unit)

• 12-bit resolution

• Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 40 MHz

• Operating modes

Scan mode (single scan mode, continuous scan mode, and 3 group scan mode)

Group A priority control (only for 3 group scan mode)

• Sampling variable

Sampling time can be set up for each channel

• Self-diagnostic function

• Double trigger mode (A/D conversion data duplicated)

• Assist on analog input disconnection detection

• A/D conversion start conditions

A software trigger, a trigger from a timer (MTU3, GPT, TMR), or an external trigger signal

• Sample-and-hold function

Sample-and-hold circuit included (3 channels for unit 1)

• Amplification of input signals by a programmable gain amplifier (1 channel for unit 0, 3 channels for

unit 1)

Amplification rate: 2.0 times, 2.5 times, 3.077 times, 3.636 times, 4.0 times, 4.444 times (total of 6

steps)

Comparator C (CMPC)

• 4 channels

• Function to compare the reference voltage and the analog input voltage

• Reference voltage: Select from among two voltages

• Analog input voltage is selectable from 4 inputs

8-bit D/A converter (DA, DAa)

• DA

1 channel

8-bit resolution

Output voltage: 0 V to VREF

Dedicated for generating comparator C reference voltage

• DAa

2 channels

8-bit resolution

Output voltage: 0 V to VREF

Can be output externally and used as comparator C reference voltage

Safety

Memory protection unit

(MPU)

• Protection area: Eight areas (max.) can be specified in the range from 0000 0000h to FFFF FFFFh.

• Minimum protection unit: 16 bytes

• Reading from, writing to, and enabling the execution access can be specified for each area.

• An address exception occurs when the detected access is not in the permitted area.

Register write protection

function

• Protects important registers from being overwritten for in case a program runs out of control.

CRC calculator (CRC)

• CRC code generation for arbitrary amounts of data in 8-bit units

• Select any of three generating polynomials:

X8 + X2 + X + 1, X16 + X15 + X2 + 1, or X16 + X12 + X5 + 1

• Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.

Main clock oscillation stop

function

• Main clock oscillation stop detection: Available

Clock frequency accuracy

measurement circuit (CAC)

• Monitors the clock output from the main clock oscillator, high-speed on-chip oscillator, low-speed on-

chip oscillator, the PLL frequency synthesizer, IWDT-dedicated on-chip oscillator, and PCLKB.

Data operation circuit (DOC) The function to compare, add, or subtract 16-bit data

Power supply voltages/Operating frequencies

VCC = 2.7 to 5.5 V: 80 MHz

Packages

100-pin LFQFP 0.5 mm pitch

80-pin LQFP 0.65 mm pitch

80-pin LFQFP 0.5 mm pitch

64-pin LFQFP 0.5 mm pitch

On-chip debugging system

E1 emulator (FINE interface)

Table 1.1

Outline of Specifications (4/4)

Classification

Module/Function

Description

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