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R7FS128783A01CFM Datasheet(PDF) 5 Page - Renesas Technology Corp |
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R7FS128783A01CFM Datasheet(HTML) 5 Page - Renesas Technology Corp |
5 / 107 page R01DS0309EU0100 Rev.1.00 Page 5 of 107 Mar 10, 2017 S128 1. Overview 1. Overview The S128 MCU integrates multiple series of software- and pin-compatible ARM®-based 32-bit MCUs that share a common set of Renesas peripherals to facilitate design scalability and efficient platform-based product development. Based on the energy-efficient ARM Cortex®-M0+ 32-bit core, this MCU is particularly suited for cost-sensitive and low- power applications. The MCU in this series has the following features: Up to 256 KB code flash memory 24-KB SRAM Capacitive Touch Sensing Unit (CTSU) 14-bit A/D Converter (ADC14) 8-bit D/A Converter (DAC8) Security features. 1.1 Function Outline Table 1.1 ARM core Feature Functional description ARM Cortex-M0+ Maximum operating frequency: up to 32 MHz ARM Cortex-M0+ - Revision: r0p1-00rel0 - ARMv6-M architecture profile - Single-cycle integer multiplier. ARM Memory Protection Unit (MPU) - ARMv6 Protected Memory System Architecture - 8 protection regions. SysTick timer - Driven by LOCO clock. Table 1.2 Memory Feature Functional description Code flash memory Maximum 256 KB code flash memory. See section 42, Flash Memory in User’s Manual. Data flash memory 4 KB data flash memory. See section 42, Flash Memory in User’s Manual. Option-setting memory The option-setting memory determines the state of the MCU after a reset. See section 6, Option-Setting Memory in User’s Manual. SRAM On-chip high-speed SRAM with either parity bit or Error Correction Code (ECC). See section 41, SRAM in User’s Manual. Table 1.3 System (1 of 2) Feature Functional description Operating mode Two operating modes: Single-chip mode SCI boot mode. See section 3, Operating Modes in User’s Manual. |
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